The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2016

Filed:

Jun. 18, 2014
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Shao-Ming Koh, Clifton Park, NY (US);

Guillaume Bouche, Albany, NY (US);

Jing Wan, Malta, NY (US);

Andy C. Wei, Queensbury, NY (US);

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/66 (2006.01); B82Y 10/00 (2011.01); B82Y 40/00 (2011.01); H01L 29/775 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66439 (2013.01); B82Y 10/00 (2013.01); B82Y 40/00 (2013.01); H01L 29/0673 (2013.01); H01L 29/6653 (2013.01); H01L 29/66575 (2013.01); H01L 29/66636 (2013.01); H01L 29/775 (2013.01);
Abstract

A method of forming a nanowire device includes forming semiconductor material layers above a semiconductor substrate, forming a gate structure above the semiconductor material layers, forming a first sidewall spacer adjacent to the gate structure and forming a second sidewall spacer adjacent to the first sidewall spacer. The method further includes patterning the semiconductor material layers such that each layer has first and second exposed end surfaces. The gate structure, the first sidewall spacer, and the second sidewall spacer are used in combination as an etch mask during the patterning process. The method further includes removing the first and second sidewall spacers, thereby exposing at least a portion of the patterned semiconductor material layers. The method further includes forming doped extension regions in at least the exposed portions of the patterned semiconductor material layers after removing the first and second sidewall spacers.


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