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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9660075 B1

PDFFull Text
Date of Patent:
May. 23, 2017

Filed:

Feb. 24, 2016

Integrated circuits with dual silicide contacts and methods for fabricating same

Applicant:

Globalfoundries, Inc., Grand Cayman, KY;

Inventors:

Shao Ming Koh, Clifton Park, NY (US);

Guillaume Bouche, Malta, NY (US);

Jeremy A. Wahl, Malta, NY (US);

Andy C. Wei, Queensbury, NY (US);

Assignee:

GLOBALFOUNDRIES, INC., Grand Cayman, KY;

Attorney:

Lorenz & Kopf, LLP

Primary Examiner:

Asok K Sarkar

Int. Cl.
CPC ...
H01L 21/84 (2006.01); H01L 29/78 (2006.01); H01L 27/092 (2006.01); H01L 21/311 (2006.01); H01L 29/45 (2006.01); H01L 21/8238 (2006.01); H01L 29/16 (2006.01); H01L 29/167 (2006.01); H01L 29/161 (2006.01); H01L 21/02 (2006.01); H01L 29/08 (2006.01); H01L 29/24 (2006.01); H01L 29/66 (2006.01); H01L 29/417 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7839 (2013.01); H01L 21/02532 (2013.01); H01L 21/31111 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823871 (2013.01); H01L 21/845 (2013.01); H01L 27/0922 (2013.01); H01L 27/0924 (2013.01); H01L 27/1211 (2013.01); H01L 29/0847 (2013.01); H01L 29/16 (2013.01); H01L 29/161 (2013.01); H01L 29/167 (2013.01); H01L 29/24 (2013.01); H01L 29/41791 (2013.01); H01L 29/45 (2013.01); H01L 29/456 (2013.01); H01L 29/665 (2013.01); H01L 29/7848 (2013.01);
Abstract

Integrated circuits having silicide contacts with reduced contact resistance and methods for fabricating integrated circuits having silicide contacts with reduced contact resistance are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with fin structures having source/drain regions in PFET areas and in NFET areas. The method includes selectively forming a contact resistance modulation material on the source/drain regions in the PFET areas. Further, the method includes depositing a band-edge workfunction metal overlying the source/drain regions in the PFET areas and in the NFET areas.

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