Globalfoundries Inc.

Andy C Wei

Guillaume Bouche

Shao Ming Koh

Jing Wan

Ruilong Xie

Dae Geun Yang

Francis M Tambwe

Xiuyu Cai

Peter Baars

Jin Ping Liu

Zhenyu Hu

Qi Zhang

Jeremy Austin Wahl

Richard J Carter

Akshey Sehgal

Stefan Flachowsky

Jagar Singh

Xiang Hu

Richard Carter

Sudharshanan Raghunathan

Sruthi Muralidharan

Jason Eugene Stephens

Mahadeva Iyer Natarajan

Ralf Illgen

Tom Herrmann

Daniel T Pham

Amaury Gendron

Seung Yeon Kim

Dae-han Choi

Teck Jung Tang

Tim Baldauf

Mariappan Hariharaputhiran

Amy L Child

Jeong Soo Kim

Shao-Ming Koh

Gopal Srinivasan

Chanro Park

Ajey Poovannummoottil Jacob

Bin Yang

Hoon Sik Kim

Hiroaki Niimi

Dinesh Somasekhar

Kisik Choi

Thilo Scheiper

Ali Keshavarzi

Michael John Hargrove

William James Taylor, Jr

Nicholas V Licausi

Frank Scott Johnson

Kwan-Yong Lim

Manjunatha Govinda Prabhu

Ryan Ryoung-Han Kim

Scott Beasor

Robert J Miller

Youngtag Woo

Hongliang Shen

Taejoon Han

Deniz Elizabeth Civay

Vikrant Kumar Chauhan

Sandeep Gaan

Anil Kumar

Lun Zhao

Rama Kambhampati

Tien-Ying Luo

Erik Geiss

Erik P Geiss

David Michael Permana

Cuiqin Xu

Churamani Gaire

Lakshmanan H Vanamurthy

Jerome F Wandell

Subi Kengeri

Bamidele S Allimi

Srinvasa Banna

Francis C Tambwe

Jagannathan Vasudevan

Sudharshanan Raghunthathan

Sridhar Kuchibhatla

A method includes forming at least one fin in a semiconductor substrate. A fin spacer is formed on at least a first portion of the at least one fin. The fin spacer has an upper surface. The at least one fin is recessed to thereby define a recessed fin with a recessed upper surface that it is at a level below the upper surface of the fin spacer. A first epitaxial material is formed on the recessed fin. A lateral extension of the first epitaxial material is constrained by the fin spacer. A cap layer is formed on the first epitaxial material. The fin spacer is removed. The cap layer protects the first epitaxial material during the removal of the fin spacer.

Cap layer for spacer-constrained epitaxially grown material on fins of a FinFET device

A method of lithographically cutting a Mx line before the Mx line is lithographically defined by patterning and the resulting 2DSAV device are provided. Embodiments include forming an a-Si dummy metal layer over a SiOlayer; forming a first softmask stack over the a-Si dummy metal layer; patterning a plurality of vias through the first softmask stack down to the SiOlayer; removing the first soft mask stack; forming first and second etch stop layers over the a-Si dummy metal layer, the first etch stop layer formed in the plurality of vias; forming a-Si mandrels on the second etch stop layer; forming oxide spacers on opposite sides of each a-Si mandrel; removing the a-Si mandrels; forming a-Si dummy metal lines in the a-Si dummy metal layer below the oxide spacers; and forming a SiOC layer between the a-Si dummy metal lines.

Cut first alternative for 2D self-aligned via

A method includes forming first and second contact openings in a first dielectric layer. At least the first contact opening is at least partially lined with a liner layer. A first conductive feature is formed in the first contact opening and a second conductive feature is formed in the second contact opening. A portion of the liner layer adjacent a top surface of the first dielectric layer is removed to define a recess. A barrier layer is formed above the first dielectric layer and in the recess. The barrier layer has a first dielectric constant greater than a second dielectric constant of the first dielectric layer. A second dielectric layer is formed above the barrier layer. A third conductive feature is formed embedded in the second dielectric layer and contacting the second conductive feature.

Methods of forming a high-k contact liner to improve effective via separation distance and the resulting devices

One method includes forming a plurality of first trenches in a semiconductor substrate to thereby define a plurality of initial fins in the substrate, removing at least one, but less than all, of the plurality of initial fins, forming a fin protection layer on at least the sidewalls of the remaining initial fins, with the fin protection layer in position, performing an etching process to extend a depth of the first trenches to thereby define a plurality of final trenches with a final trench depth, wherein the final trenches define a plurality of final fin structures that each comprise an initial fin, removing the fin protection layer, and forming a recessed layer of insulating material in the final trenches, wherein the recessed layer of insulating material has a recessed surface that exposes a portion of the final fin structures.

Methods of forming fins for FinFET semiconductor devices and the selective removal of such fins

Integrated circuits having silicide contacts with reduced contact resistance and methods for fabricating integrated circuits having silicide contacts with reduced contact resistance are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with fin structures having source/drain regions in PFET areas and in NFET areas. The method includes selectively forming a contact resistance modulation material on the source/drain regions in the PFET areas. Further, the method includes depositing a band-edge workfunction metal overlying the source/drain regions in the PFET areas and in the NFET areas.

Integrated circuits with dual silicide contacts and methods for fabricating same

An inverted contact and methods of fabrication are provided. A sacrificial layer is patterned in an inverted trapezoid shape, and oxide is deposited around the pattern. The sacrificial layer is removed, and a metal contact material is deposited, taking an inverted-trapezoid shape. Embodiments of the present invention provide an inverted contact, having a wider base and a narrower top. The wider base provides improved electrical contact to the underlying active area. The narrower top allows for closer placement of adjacent contacts, serving to increase overall circuit density of an integrated circuit.

Inverted contact

Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures.

FinFET devices comprising a dielectric layer/CMP stop layer/hardmask/etch stop layer/gap-fill material stack

A device disclosed herein includes a plurality of spaced-apart fin structures formed in a semiconductor substrate so as to define an alignment/overlay mark trench. An alignment/overlay mark includes at least one insulating material positioned within the alignment/overlay mark trench. The alignment/overlay mark is devoid of any of the fin structures.

Methods of forming alignment marks and overlay marks on integrated circuit products employing FinFET devices and the resulting alignment/overlay mark

Approaches for enabling uniform epitaxial (epi) growth in an epi junction area of a semiconductor device (e.g., a fin field effect transistor device) are provided. Specifically, a semiconductor device is provided including a dummy gate and a set of fin field effect transistors (FinFETs) formed over a substrate; a spacer layer formed over the dummy gate and each of the set of FinFETs; and an epi material formed within a set of recesses in the substrate, the set of recesses formed prior to removal of an epi block layer over the dummy gate.

Epitaxial block layer for a fin field effect transistor device

A method includes forming a first dielectric layer having at least one conductive feature embedded therein. A first plurality of conductive lines embedded in a second dielectric layer disposed above the first dielectric layer is formed. A first conductive line in the plurality of conductive lines contacts the conductive feature. The first conductive line is etched using a first etch mask to define a conductive via portion and a recessed line portion in the first conductive line. A second plurality of conductive lines embedded in a third dielectric layer disposed above the second dielectric layer is formed. A second conductive line in the second plurality of conductive lines contacts the conductive via portion and the third dielectric layer directly contacts the second dielectric layer.

Self-aligned via process flow

A method of forming a nanowire device includes patterning a plurality of semiconductor material layers such that each layer has first and second exposed end surfaces. The method further includes forming doped extension regions in the first and second exposed end surfaces of the semiconductor material layers. The method further includes, after forming the doped extension regions, forming epi semiconductor material in source and drain regions of the device.

Methods of forming nanowire devices with doped extension regions and the resulting devices

Devices and methods for forming semiconductor devices with wider FinFETs for higher tunability of the varactor are provided. One method includes, for instance: obtaining an intermediate semiconductor device; applying a spacer layer over the semiconductor device; etching the semiconductor device to remove at least a portion of the spacer layer to expose the plurality of mandrels; removing the mandrels; etching the semiconductor device to remove a portion of the dielectric layer; forming at least one fin; and removing the spacer layer and the dielectric layer. One intermediate semiconductor device includes, for instance: a substrate; a dielectric layer over the substrate; a plurality of mandrels formed on the dielectric layer, the mandrels including a first set of mandrels and a second set of mandrels, wherein the first set of mandrels have a width twice as large as the second set of mandrels; and a spacer layer applied over the mandrels.

Devices and methods of forming higher tunability FinFET varactor

A method of forming a nanowire device includes forming semiconductor material layers above a semiconductor substrate, forming a gate structure above the semiconductor material layers, forming a first sidewall spacer adjacent to the gate structure and forming a second sidewall spacer adjacent to the first sidewall spacer. The method further includes patterning the semiconductor material layers such that each layer has first and second exposed end surfaces. The gate structure, the first sidewall spacer, and the second sidewall spacer are used in combination as an etch mask during the patterning process. The method further includes removing the first and second sidewall spacers, thereby exposing at least a portion of the patterned semiconductor material layers. The method further includes forming doped extension regions in at least the exposed portions of the patterned semiconductor material layers after removing the first and second sidewall spacers.

Methods of forming nanowire devices with spacers and the resulting devices

A method includes forming a plurality of sacrificial lines embedded in a first dielectric layer. A line merge opening and a line cut opening are formed in a hard mask layer formed above the first dielectric layer. Portions of the first dielectric layer exposed by the line merge opening are removed to define a line merge recess. A portion of a selected sacrificial line exposed by the line cut opening is removed to define a line cut recess between first and second segments of the selected sacrificial line. A second dielectric layer is formed in the line cut recess. The hard mask is removed. The plurality of sacrificial lines is replaced with a conductive material to define at least one line having third and fourth segments in locations previously occupied by the first and second segments and to define a line-merging conductive structure in the line merge recess.

Forming merged lines in a metallization layer by replacing sacrificial lines with conductive lines

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Queensbury, NY, United States of America

Andy C Wei