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Sunnyvale, CA, United States of America

Vantis Corporation

USPTO Granted Patents = 67

Forward Citations = 1,843

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24 inventors (with patents filed for the assignee):

Bradley A Sharpe-Geisler (35 out of 104 patents)

Om P Agrawal (23 out of 143 patents)

Sunil D Mehta (21 out of 96 patents)

4. Herman M Chang (17 out of 25 patents)

5. Giap H Tran (16 out of 30 patents)

6. Bai Yen Nguyen (14 out of 39 patents)

7. Xiao-yu Li (11 out of 29 patents)

8. Steven J Fong (7 out of 13 patents)

9. Hyeon-Seag Kim (5 out of 5 patents)

10. Christopher O Schmidt (3 out of 9 patents)

11. Jack Tim Wong (3 out of 20 patents)

12. Stewart G Logie (3 out of 19 patents)

13. Xiao-Yu Li (2 out of 2 patents)

14. Brad Sharpe-Geisler (1 out of 30 patents)

15. Minh Van Ngo (1 out of 292 patents)

Core Competencies:

Non-Volatile Memory

FPGA Architecture

Semiconductor Processes

Floating Gate Memory

EEPROM Cells

Programmable Logic Devices

Variable Grain Architecture

High Voltage Switch

Interconnect Networks

Dual Port SRAM

Electrostatic Discharge Protection

Data Retention

67 patents: Sort by Forward Citations

1. 6455912 - Process for manufacturing shallow trenches filled with dielectric material having low mechanical stress (2002-09-24),

2. 6424000 - Floating gate memory apparatus and method for selected programming thereof (2002-07-23),

3. 6413826 - Gate insulator process for nanometer MOSFETS (2002-07-02),

4. 6404006 - EEPROM cell with tunneling across entire separated channels (2002-06-11),

5. 6380759 - Variable grain architecture for FPGA integrated circuits (2002-04-30),

6. 6359466 - Circuitry to provide fast carry (2002-03-19),

7. 6353352 - Clock tree topology (2002-03-05),

8. 6351157 - Output buffer for making a high voltage (5.0 volt) compatible input/output in a low voltage (2.5 volt) semiconductor process (2002-02-26),

9. 6326808 - Inversion of product term line before or logic in a programmable logic device (PLD) (2001-12-04),

10. 6326663 - Avalanche injection EEPROM memory cell with P-type control gate (2001-12-04),

11. 6297128 - Process for manufacturing shallow trenches filled with dielectric material having low mechanical stress (2001-10-02),

12. 6294811 - Two transistor EEPROM cell (2001-09-25),

13. 6294810 - EEPROM cell with tunneling at separate edge and channel regions (2001-09-25),

14. 6294809 - Avalanche programmed floating gate memory cell structure with program element in polysilicon (2001-09-25),

15. 6292930 - Methods for configuring FPGA's having variable grain blocks and shared logic for providing time-shared access to interconnect resources (2001-09-18),

Company Overview

Vantis Corporation, based in Sunnyvale, California, specializes in the development of advanced FPGA integrated circuits. The company focuses on innovative technologies such as non-volatile memory and floating gate memory, enhancing the capabilities of programmable logic devices. Vantis is dedicated to pushing the boundaries of semiconductor processes and FPGA architecture, with a particular emphasis on variable grain architecture and high voltage switch technologies. Their expertise positions them as a key player in the evolving landscape of semiconductor solutions.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 20 2026

67 Patents

#75 in Sunnyvale, CA

#1,270 in California

#5,461 in US

#11,040 in the World

Sunnyvale, CA, United States of America

Vantis Corporation

Forward Citations = 1,843

24 inventors:

Bradley A Sharpe-Geisler (35 out of 104 patents)

Om P Agrawal (23 out of 143 patents)

Sunil D Mehta (21 out of 96 patents)

4. Herman M Chang (17 out of 25 patents)

5. Giap H Tran (16 out of 30 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Vantis Corporation. Retrieved from https://idiyas.com/company/vantis

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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