The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 05, 2002
Filed:
Nov. 25, 1998
Applicant:
Inventor:
Bradley A. Sharpe-Geisler, San Jose, CA (US);
Assignee:
Vantis Corporation, Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 3/00 ;
U.S. Cl.
CPC ...
H03K 3/00 ;
Abstract
A clock tree topology distributes a clock signal from a single input terminal to three terminals with an equal phase delay. The topology includes four lines connected together at a first end with adjacent lines forming right angles. A second end of the line forms the clock signal input terminal . A second end of the remaining lines are connected to first ends of lines . Second ends of the lines form the terminals . A right angle is formed between each of the lines and the respective one of the lines to which it connects.