The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 26, 2002
Filed:
Apr. 13, 2000
Bradley A. Sharpe-Geisler, San Jose, CA (US);
Vantis Corporation, Sunnyvale, CA (US);
Abstract
An output buffer includes transistors which tolerate a maximum gate to source, gate to drain, or drain to source voltage (“the maximum tolerable voltage”), such as 2.7 volts, the transistors being configured to produce an output voltage significantly higher than the maximum tolerable voltage. The output buffer includes pull up transistors having source to drain paths connected in series to connect a voltage supply higher than the maximum tolerable voltage to the buffer output. The buffer further includes pull down transistors having source to drain paths connected in series to connect the buffer output to ground. The buffer further includes power supply circuitry to apply gate voltages to the pull up and pull down transistors so that the voltage potential from the source to drain of each of the pull up and pull down transistors is less than the maximum tolerable voltage. The power supply circuitry further controls gate voltages so that neither the gate to source, nor the gate to drain voltage for each of the pull up and pull down transistors exceeds the maximum tolerable voltage. Additionally, the power supply circuitry is itself configured so that voltage across leads of its transistor does not exceed the maximum tolerable voltage.