The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 04, 2001
Filed:
Dec. 03, 1999
Mathew Fisk, San Jose, CA (US);
Apurva Patel, Fremont, CA (US);
Bradley Sharpe-Geisler, San Jose, CA (US);
Vantis Corporation, San Jose, CA (US);
Abstract
A PLD circuit configuration is provided to use less product term lines than a typical PLD to perform an OR operation without using an OR gate. In one embodiment, an inverter is provided between the output of one product term line and the input of an OR gate. The inverter enables the one product term provided to it to provide an OR operation. This is because when two or more elements are ANDed in a product term, inverting the product term creates an OR operation with the elements inverted. With an OR operation provided using a single product term and inverter, less product term lines are needed when performing some operations. In another embodiment, an OR gate output is provided to the first input of a look up table (LUT), while a single product term line is provided to a second input of the LUT. The LUT can be programmably configured to perform a number of Boolean logic functions, such as an OR gate, an XOR gate, etc. The input to the LUT can further be programmed to be inverted, enabling a single product term input to the LUT to be used where two separate product terms might otherwise be required.