Circuitry to provide fast carry

Abstract

A circuit for providing a carry operation utilizing 3-input look up tables and and subsequent logic, the circuitry being configurable to provide an adder, a subtractor, an up/down counter, a pre-loadable counter, an accumulator, and a wide gate such as a large AND gate. To provide a carry out C , a multiplexer has a first input receiving a carry in C , a select input coupled to the output of look up table and a second input coupled to the output of look up table The look up tables receive signals representing numbers A and B to be added or subtracted and ADD/SUB indicating if addition or subtraction is desired. The look up table is programmed to provide A (+)B , while look up table is programmed to provide A *B , (+) indicating a Boolean exclusive OR, and * a Boolean AND. With ADD selected, multiplexer provides the carry out C of the operation A +B +C . With SUB selected, a 2's complement of B is done before adding in the look up tables. The carry provided by multiplexer is buffered by only one inverter. To provide a result of an addition or subtraction operation, S , a multiplexer has a first input receiving C , a second input receiving the inverse of C , and a select input receiving the output of look up table An up/down counter, an accumulator and a preloadable counter can be formed by registering each S output back to its corresponding A input. Additional components ( ) can be included to provide wide gating.