The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 18, 2001
Filed:
Jun. 22, 2000
Applicant:
Inventors:
Om P. Agrawal, Los Altos, CA (US);
Bradley A. Sharpe-Geisler, San Jose, CA (US);
Herman M. Chang, Cupertino, CA (US);
Giap H. Tran, San Jose, CA (US);
Assignee:
Vantis Corporation, Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ; H03K 1/9173 ; H03K 1/9177 ;
U.S. Cl.
CPC ...
G06F 1/750 ; H03K 1/9173 ; H03K 1/9177 ;
Abstract
A Variable Grain Architecture (VGA) includes a shared output component (SOC) that may be used for outputting different signals onto a shared longline within an FPGA. Plural VGB's make shared use of the SOC to out respective function signals to the shared longline.
Quick Actions:
Agrawal, Om. (2001). Methods for configuring fpga's having variable grain blocks and shared logic for providing time-shared access to interconnect resources (U.S. Patent No. 6292930). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6292930
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