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San Jose, CA, United States of America

Ultratech, Inc.

USPTO Granted Patents = 138

% Expired Patents = 71.0

EPO Patents = 4

Trademarks = 8

Forward Citations = 1,296

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113 inventors (with patents filed for the assignee):

Andrew M Hawryluk (38 out of 64 patents)

David A Markle (24 out of 81 patents)

Serguei Anikitchev (15 out of 30 patents)

4. Yun Yu Wang (13 out of 257 patents)

5. Somit Talwar (12 out of 34 patents)

6. Boris Grek (11 out of 19 patents)

7. Ganesh Sundaram (9 out of 10 patents)

8. Arthur W Zafiropoulo (9 out of 9 patents)

9. Emily M True (8 out of 8 patents)

10. James McWhirter (8 out of 9 patents)

11. Michael O Thompson (7 out of 30 patents)

12. Romeo I Mercado (6 out of 26 patents)

13. Shiyu Zhang (6 out of 13 patents)

14. Jill Svenja Becker (6 out of 14 patents)

15. Igor Landau (5 out of 7 patents)

Core Competencies:

Laser Annealing

Optical Systems

Atomic Layer Deposition

Gallium Nitride

Semiconductor Processing

Heteroepitaxial Layers

Thin Film Deposition

Photolithography

Electrical Connectors

Wafer Processing

Solder Interconnects

Plasma Processing

138 patents: Sort by Forward Citations

1. 12725956 - Electrical connector comprising two pluralities of flexible strips, one surrounding the other in an inserted configuration of the connector (2026-09-01),

2. 12562522 - Electrical connector comprising a user protective system (2026-02-24),

3. 12555949 - Electrical connector comprising two sleeves defining a closed equipotential cavity around a contact zone (2026-02-17),

4. 11600949 - Assembly comprising a first connector, a second connector and a coding system selectively allowing connection (2023-03-07),

5. 10468290 - Wafer chuck apparatus with micro-channel regions (2019-11-05),

6. 10353208 - High-efficiency line-forming optical systems and methods using a serrated spatial filter (2019-07-16),

7. 10351950 - Plasma enhanced ALD system (2019-07-16),

8. 10316406 - Methods of forming an ALD-inhibiting layer using a self-assembled monolayer (2019-06-11),

9. 10269662 - Scanning methods for focus control for lithographic processing of reconstituted wafers (2019-04-23),

10. 10249491 - Method and apparatus for forming device quality gallium nitride layers on silicon substrates (2019-04-02),

11. 10090153 - Formation of heteroepitaxial layers with rapid thermal processing to remove lattice dislocations (2018-10-02),

12. 10083843 - Laser annealing systems and methods with ultra-short dwell times (2018-09-25),

13. 10032883 - Silicon germanium heterojunction bipolar transistor structure and method (2018-07-24),

14. 10016843 - Systems and methods for reducing pulsed laser beam profile non-uniformities for laser annealing (2018-07-10),

15. 9960036 - Method and apparatus for forming device quality gallium nitride layers on silicon substrates (2018-05-01),

Company Overview

Ultratech, Inc., based in San Jose, CA, specializes in advanced laser annealing systems that are pivotal in semiconductor processing. The company focuses on core technologies such as optical systems, atomic layer deposition, and thin film deposition, contributing significantly to the development of gallium nitride and heteroepitaxial layers. Ultratech's innovations play a crucial role in enhancing the performance and efficiency of semiconductor devices, catering to the evolving needs of the technology sector.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 20 2026

138 Patents

#87 in San Jose, CA

#631 in California

#2,820 in US

#5,868 in the World

San Jose, CA, United States of America

Ultratech, Inc.

Forward Citations = 1,296

113 inventors:

Andrew M Hawryluk (38 out of 64 patents)

David A Markle (24 out of 81 patents)

Serguei Anikitchev (15 out of 30 patents)

4. Yun Yu Wang (13 out of 257 patents)

5. Somit Talwar (12 out of 34 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Ultratech, Inc.. Retrieved from https://idiyas.com/company/ultratech

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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