The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 24, 2018

Filed:

Aug. 13, 2016
Applicant:

Ultratech, Inc., San Jose, CA (US);

Inventors:

Oleg Gluschenkov, Poughkeepsie, NY (US);

Rajendran Krishnasamy, Essex Junction, VT (US);

Kathryn T. Schonenberg, Wappingers Falls, NY (US);

Assignee:

Ultratech, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/66 (2006.01); H01L 29/08 (2006.01); H01L 29/737 (2006.01); H01L 21/225 (2006.01); H01L 21/265 (2006.01); H01L 21/324 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66242 (2013.01); H01L 21/2253 (2013.01); H01L 21/26513 (2013.01); H01L 21/324 (2013.01); H01L 29/0821 (2013.01); H01L 29/0826 (2013.01); H01L 29/1004 (2013.01); H01L 29/7378 (2013.01);
Abstract

Disclosed is an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology.


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