The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2019

Filed:

Dec. 07, 2017
Applicant:

Ultratech, Inc., San Jose, CA (US);

Inventors:

Paul M. Bischoff, Livermore, CA (US);

Emily M. True, San Ramon, CA (US);

Raymond Ellis, Aptos, CA (US);

A. J. Crespin, San Jose, CA (US);

Assignee:

Ultratech, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); H01L 23/00 (2006.01); H01L 21/67 (2006.01); H01L 21/68 (2006.01); G03F 7/20 (2006.01); G03F 1/36 (2012.01); H01L 21/027 (2006.01); G03F 9/00 (2006.01);
U.S. Cl.
CPC ...
H01L 22/20 (2013.01); G03F 1/36 (2013.01); G03F 7/20 (2013.01); G03F 9/7034 (2013.01); G03F 9/7046 (2013.01); H01L 21/0274 (2013.01); H01L 21/67259 (2013.01); H01L 21/681 (2013.01); H01L 23/00 (2013.01); H01L 24/02 (2013.01); H01L 24/96 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/13025 (2013.01);
Abstract

A method of processing a reconstituted wafer that supports IC chips includes operably disposing the reconstituted wafer in a lithography tool that has a depth of focus and a focus plane and that defines exposure fields on the reconstituted wafer, wherein each exposure field includes at least one of the IC chips. The method also includes scanning the reconstituted wafer with a line scanner to measure a surface topography of the reconstituted wafer as defined by the IC chips. The method also includes, for each exposure field: i) adjusting a position and/or an orientation of the reconstituted wafer so that a photoresist layers of the IC chips within the given exposure field fall within the depth of focus; and ii) performing an exposure with the lithography tool to pattern the photoresist layers of the IC chips in the given exposure field.


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