For the Inventor, By the Inventor

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San Jose, CA, United States of America

Silicon Genesis Corporation

USPTO Granted Patents = 150

% Expired Patents = 40.0

EPO Patents = 3

Forward Citations = 8,340

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35 inventors (with patents filed for the assignee):

Francois J Henley (107 out of 149 patents)

Nathan W Cheung (53 out of 59 patents)

Igor J Malik (17 out of 19 patents)

4. Sien G Kang (12 out of 15 patents)

5. Michael I Current (11 out of 16 patents)

6. Harry Robert Kirk (11 out of 11 patents)

7. Philip James Ong (11 out of 11 patents)

8. Theodore E Fong (10 out of 10 patents)

9. Michael A Bryan (10 out of 28 patents)

10. Chung M Chan (10 out of 30 patents)

11. Paul K Chu (6 out of 7 patents)

12. William George En (5 out of 68 patents)

13. James Andrew Sullivan (4 out of 6 patents)

14. Sharon N Farrens (4 out of 4 patents)

15. James K Kai (4 out of 156 patents)

Core Competencies:

Layer Transfer

Three-Dimensional Integrated Circuits

Semiconductor Devices

Controlled Cleaving

Sapphire Layer Cleaving

Strained Silicon

Solar Cells

Implantation Techniques

Optoelectronic Devices

Silicon Ingots

Thin Films

Wafering Techniques

150 patents: Sort by Forward Citations

1. 12582012 - Method of forming semiconductor device using high stress cleave plane (2026-03-17),

2. 12176326 - Method of forming semiconductor device using high stress cleave plane (2024-12-24),

3. 11901351 - Three dimensional integrated circuit with lateral connection layer (2024-02-13),

4. 11626392 - Method of forming semiconductor device using range compensating material (2023-04-11),

5. 11444221 - Layer transfer of films utilizing controlled shear region (2022-09-13),

6. 11410984 - Three dimensional integrated circuit with lateral connection layer (2022-08-09),

7. 10923459 - Three dimensional integrated circuit (2021-02-16),

8. 10804252 - Three dimensional integrated circuit (2020-10-13),

9. 10683588 - Shaped silicon ingot using layer transfer (2020-06-16),

10. 10573627 - Three dimensional integrated circuit (2020-02-25),

11. 10087551 - Method and device for slicing a shaped silicon ingot using layer transfer (2018-10-02),

12. 10049915 - Three dimensional integrated circuit (2018-08-14),

13. 9704835 - Three dimensional integrated circuit (2017-07-11),

14. 9640711 - Substrate cleaving under controlled stress conditions (2017-05-02),

15. 9460908 - Method and device for slicing a shaped silicon ingot using layer transfer (2016-10-04),

Company Overview

Silicon Genesis Corporation, based in San Jose, CA, specializes in advanced semiconductor fabrication technologies. The company focuses on innovative processes such as layer transfer and controlled cleaving, which are essential for the development of three-dimensional integrated circuits and high-performance semiconductor devices. Their expertise extends to strained silicon and sapphire layer cleaving, contributing to advancements in solar cell technology and various implantation techniques, positioning them as a key player in the semiconductor industry.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 13 2026

150 Patents

#80 in San Jose, CA

#581 in California

#2,626 in US

#5,441 in the World

San Jose, CA, United States of America

Silicon Genesis Corporation

Forward Citations = 8,340

35 inventors:

Francois J Henley (107 out of 149 patents)

Nathan W Cheung (53 out of 59 patents)

Igor J Malik (17 out of 19 patents)

4. Sien G Kang (12 out of 15 patents)

5. Michael I Current (11 out of 16 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Silicon Genesis Corporation. Retrieved from https://idiyas.com/company/silicon-genesis

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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