The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 2022

Filed:

Oct. 08, 2021
Applicant:

Silicon Genesis Corporation, Fremont, CA (US);

Inventors:

Michael I. Current, San Jose, CA (US);

Theodore E. Fong, Pleasanton, CA (US);

Assignee:

Silicon Genesis Corporation, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/78 (2006.01); H01L 25/00 (2006.01); H01L 21/768 (2006.01); H01L 21/48 (2006.01); H01L 25/065 (2006.01); H01L 21/60 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/50 (2013.01); H01L 21/486 (2013.01); H01L 21/60 (2021.08); H01L 21/76802 (2013.01); H01L 21/78 (2013.01); H01L 24/95 (2013.01); H01L 25/0657 (2013.01);
Abstract

Forming a 3DIC includes providing a lower device structure comprising a first substrate with a circuit layer, providing an interconnect network layer having an interconnect structure with a first coupled to a second plurality of electrodes by connection structures on a semiconductor substrate, the first plurality of electrodes being exposed on a first surface of the interconnect layer, implanting ions through the interconnect structure to form a cleave plane in the semiconductor substrate, bonding the interconnect structure to the lower device structure so that electrodes of the first plurality of electrodes are coupled to corresponding electrodes on the lower device structure, cleaving the substrate of the bonded interconnect layer at the cleave plane, removing material from the semiconductor substrate until the second plurality of electrodes is exposed, and bonding an upper device layer to the interconnect structure.


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