The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 11, 2023

Filed:

Feb. 12, 2021
Applicant:

Silicon Genesis Corporation, Fremont, CA (US);

Inventors:

Theodore E. Fong, Pleasanton, CA (US);

Michael I. Current, San Jose, CA (US);

Assignee:

Silicon Genesis Corporation, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/10 (2006.01); H01L 21/822 (2006.01); H01L 25/00 (2006.01); H01L 21/762 (2006.01); H01L 23/00 (2006.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
H01L 25/105 (2013.01); H01L 21/76254 (2013.01); H01L 21/8221 (2013.01); H01L 24/83 (2013.01); H01L 24/94 (2013.01); H01L 25/50 (2013.01); H01L 24/08 (2013.01); H01L 27/0688 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80 (2013.01); H01L 2224/83013 (2013.01); H01L 2224/83099 (2013.01); H01L 2225/1094 (2013.01); H01L 2924/00 (2013.01); H01L 2924/0002 (2013.01); H01L 2924/14 (2013.01);
Abstract

A method of forming a semiconductor device includes providing a semiconductor substrate with a circuit layer, forming a range compensating layer over the semiconductor substrate, the range compensating layer having a plurality of different thicknesses, each of the plurality of different thicknesses being inversely proportional to a stopping power of structures disposed under the respective thickness of the range compensating layer, implanting ions into the semiconductor substrate, the ions traveling through the range compensating layer and the circuit layer to define a cleave plane in the semiconductor substrate, removing the range compensating layer, and cleaving the semiconductor substrate at the cleave plane. The range compensating layer can be used to compensate for variations in ion penetration depth.


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