The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2017

Filed:

Jan. 11, 2016
Applicant:

Silicon Genesis Corporation, San Jose, CA (US);

Inventors:

Theodore E. Fong, Pleasanton, CA (US);

Michael I. Current, San Jose, CA (US);

Assignee:

SILICON GENESIS CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/822 (2006.01); H01L 25/10 (2006.01); H01L 21/762 (2006.01); H01L 25/00 (2006.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
H01L 25/105 (2013.01); H01L 21/76254 (2013.01); H01L 21/8221 (2013.01); H01L 25/50 (2013.01); H01L 27/0688 (2013.01); H01L 2225/1094 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A method comprises providing a first substrate having dielectric structures and conductive structures. Ions are implanted into the first substrate, the ions traveling through the dielectric structures and the conductive structures to define a cleave plane in the first substrate. The first substrate is cleaved at the cleave plane to obtain a cleaved layer having the dielectric structure and the conductive structures. The cleaved layer is used to form a three-dimensional integrated circuit device having a plurality of stacked integrated circuit (IC) layers, the cleaved layer being one of the stacked IC layers.


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