For the Inventor, By the Inventor

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Bloomington, MN, United States of America

Polar Semiconductor, Inc.

USPTO Granted Patents = 35

% Expired Patents = 37.1

Trademarks = 3

Forward Citations = 156

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33 inventors (with patents filed for the assignee):

Steven L Kosier (8 out of 15 patents)

Don Rankila (6 out of 6 patents)

Peter West (6 out of 7 patents)

4. Tatsuya Kamimura (5 out of 5 patents)

5. Gregory J Rausch (5 out of 10 patents)

6. Noel P Hoilien (5 out of 8 patents)

7. Michael J Gaboury (4 out of 28 patents)

8. Dosi Dosev (3 out of 3 patents)

9. Kurt Kimber (3 out of 5 patents)

10. Josh Wibben (3 out of 3 patents)

11. Shohei Osaka (3 out of 15 patents)

12. John Charles Beckman (3 out of 4 patents)

13. Shunsuke Fukunaga (2 out of 12 patents)

14. Thomas S Chung (2 out of 2 patents)

15. David Litfin (2 out of 4 patents)

Core Competencies:

High-Voltage MOSFET

Trench Semiconductor

Power Supply

LDMOS Transistor

Etch Stop Layer

Isolation Structures

Anti-Snapback Circuitry

Differential Level Shifter

Power Factor Correction

Photodiode Array

Bipolar Junction Transistor

Soft-Start Protection

35 patents: Sort by Forward Citations

1. 12142481 - Forming passivation stack having etch stop layer (2024-11-12),

2. 12015079 - Transistor with single termination trench having depth more than 10 microns (2024-06-18),

3. 11329147 - Insulated gate bipolar transistor with epitaxial layer formed on recombination region (2022-05-10),

4. 11264496 - Transistor with buried p-field termination region (2022-03-01),

5. 11245006 - Trench semiconductor device layout configurations (2022-02-08),

6. 10896885 - High-voltage MOSFET structures (2021-01-19),

7. 10580861 - Trench semiconductor device layout configurations (2020-03-03),

8. 10388783 - Floating-shield triple-gate MOSFET (2019-08-20),

9. 10332992 - Semiconductor device having improved trench, source and gate electrode structures (2019-06-25),

10. 10153366 - LDMOS transistor with lightly-doped annular RESURF periphery (2018-12-11),

11. 10141440 - Drift-region field control of an LDMOS transistor using biased shallow-trench field plates (2018-11-27),

12. 9899343 - High voltage tolerant bonding pad structure for trench-based semiconductor devices (2018-02-20),

13. 9818828 - Termination trench structures for high-voltage split-gate MOS devices (2017-11-14),

14. 9818742 - Semiconductor device isolation using an aligned diffusion and polysilicon field plate (2017-11-14),

15. 9704765 - Method of controlling etch-pattern density and device made using such method (2017-07-11),

Company Overview

Polar Semiconductor, Inc. is a leading provider of advanced semiconductor solutions, specializing in the design and manufacture of high-performance integrated circuits. The company focuses on developing innovative technologies for various applications, including automotive, industrial, and consumer electronics. With a commitment to quality and precision, Polar Semiconductor leverages its expertise in semiconductor fabrication to deliver cutting-edge products that meet the evolving needs of the global market. Headquartered in Bloomington, MN, the company plays a significant role in the semiconductor landscape.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 13 2026

35 Patents

#8 in Bloomington, MN

#274 in Minnesota

#9,749 in US

#19,168 in the World

Bloomington, MN, United States of America

Polar Semiconductor, Inc.

Forward Citations = 156

33 inventors:

Steven L Kosier (8 out of 15 patents)

Don Rankila (6 out of 6 patents)

Peter West (6 out of 7 patents)

4. Tatsuya Kamimura (5 out of 5 patents)

5. Gregory J Rausch (5 out of 10 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Polar Semiconductor, Inc.. Retrieved from https://idiyas.com/company/polar-semiconductor

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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