The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 11, 2017
Filed:
Jul. 31, 2015
Polar Semiconductor, Llc, Bloomington, MN (US);
Peter N. Manos, II, Eden Prairie, MN (US);
Polar Semiconductor, LLC, Bloomington, MN (US);
Abstract
A method of controlling an etch-pattern density of a polysilicon layer includes depositing polysilicon on a wafer. The method includes determining polysilicon-etch regions that include DMOS source regions within circuit-device areas of the wafer. The method includes calculating an etch area of the polysilicon-etch regions and then comparing the calculated etch area of the polysilicon-etch regions to a predetermined minimum etch area. If the calculated etch area is less than a predetermined threshold, the method adds polysilicon-etch regions within non-circuit-device areas to the determined polysilicon-etch regions within the circuit-device areas until the comparing step results in the calculated etch area of the polysilicon-etch regions being greater than the predetermined minimum etch area. The method includes etching the polysilicon from the polysilicon-etch regions in both the circuit-device areas and the non-circuit-device areas. Adding polysilicon-etch regions in non-circuit device areas can advantageously facilitate automatic process control of an etch step.