For the Inventor, By the Inventor

Enter assignee name

San Jose, CA, United States of America

Adeia Semiconductor Technologies LLC

USPTO Granted Patents = 32

EPO Patents = 4

Forward Citations = 3

Loading Chart...

Loading Chart...

50 inventors (with patents filed for the assignee):

Rajesh Katkar (10 out of 230 patents)

Cyprian Emeka Uzoh (9 out of 431 patents)

Belgacem Haba (8 out of 671 patents)

4. Javier A DeLaCruz (7 out of 137 patents)

5. Liang Wang (5 out of 127 patents)

6. Hong Shen (4 out of 73 patents)

7. Min Tao (3 out of 20 patents)

8. Patrick J Variot (3 out of 34 patents)

9. Guilian Gao (2 out of 120 patents)

10. Arkalgud R Sitaram (2 out of 59 patents)

11. Ilyas Mohammed (2 out of 285 patents)

12. Laura Wills Mirkarimi (2 out of 91 patents)

13. Richard E Perego (2 out of 145 patents)

14. Stephen L Morein (1 out of 160 patents)

15. Shaowu Huang (1 out of 51 patents)

Core Competencies:

Integrated Circuit Assemblies

Direct-Bonded Optoelectronic Devices

3D Wafer Assembly

Radio Frequency Packages

Interconnect Structures

Low Temperature Bonding

Wire Bonding

Embedded Organic Interposer

Through-Dielectric-Vias

Image Sensor Device

Non-Volatile Memory Stacks

Virtual Reality Headsets

32 patents: Sort by Forward Citations

1. RE51062 - Multiple plated via arrays of different wire heights on a same substrate (2026-10-06),

2. RE51016 - Integrated circuit assemblies with rigid layers used for protection against mechanical thinning and for other purposes, and methods of fabricating such assemblies (2026-08-25),

3. 12708053 - Direct-bonded optoelectronic devices (2026-08-11),

4. RE50965 - System and method for providing 3D wafer assembly with known-good-dies (2026-07-21),

5. 12640483 - Radio frequency device packages (2026-05-26),

6. 12635510 - Interconnect structures and methods for forming same (2026-05-19),

7. 12564086 - Structures for low temperature bonding using nanoparticles (2026-02-24),

8. 12557659 - Wire bonding method and apparatus for electromagnetic interference shielding (2026-02-17),

9. 12557615 - Methods for bonding semiconductor elements (2026-02-17),

10. 12537783 - Media appliance (2026-01-27),

11. RE50741 - Semiconductor module and portable apparatus provided with semiconductor module (2026-01-06),

12. 12500209 - Embedded organic interposer for high bandwidth (2025-12-16),

13. 12476212 - 3D-interconnect (2025-11-18),

14. 12425696 - Emulated television tuner (2025-09-23),

15. 12394728 - Method of forming a region shielding within a package of a microelectronic device (2025-08-19),

Company Overview

Adeia Semiconductor Technologies LLC, based in San Jose, California, specializes in advanced semiconductor solutions that drive innovation across various technology sectors. The company focuses on developing cutting-edge technologies that enhance performance and efficiency in electronic devices. With a strong emphasis on research and development, Adeia is committed to pushing the boundaries of semiconductor capabilities, catering to diverse applications in consumer electronics, telecommunications, and beyond.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 13 2026

32 Patents

#252 in San Jose, CA

#2,533 in California

#10,599 in US

#20,671 in the World

San Jose, CA, United States of America

Adeia Semiconductor Technologies LLC

Forward Citations = 3

50 inventors:

Rajesh Katkar (10 out of 230 patents)

Cyprian Emeka Uzoh (9 out of 431 patents)

Belgacem Haba (8 out of 671 patents)

4. Javier A DeLaCruz (7 out of 137 patents)

5. Liang Wang (5 out of 127 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Adeia Semiconductor Technologies LLC. Retrieved from https://idiyas.com/company/adeia-semiconductor-technologies

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

Loading…