The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 25, 2026
Filed:
Sep. 13, 2024
Adeia Semiconductor Technologies Llc, San Jose, CA (US);
Guilian Gao, Campbell, CA (US);
Cyprian Emeka Uzoh, San Jose, CA (US);
Charles G. Woychik, San Jose, CA (US);
Hong Shen, Palo Alto, CA (US);
Arkalgud R. Sitaram, Cupertino, CA (US);
Liang Wang, Milpitas, CA (US);
Akash Agrawal, San Jose, CA (US);
Rajesh Katkar, Milpitas, CA (US);
Adeia Semiconductor Technologies LLC, San Jose, CA (US);
Abstract
Die () and/or undiced wafers and/or multichip modules (MCMs) are attached on top of an interposer () or some other structure (e.g. another integrated circuit) and are covered by an encapsulant (). Then the interposer is thinned from below. Before encapsulation, a layer () more rigid than the encapsulant is formed on the interposer around the die to reduce or eliminate interposer dishing between the die when the interposer is thinned by a mechanical process (e.g. CMP). Other features are also provided.