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For the Inventor, By the Inventor

San Jose, CA, United States of America

Akash Agrawal

This inventor holds 16 USPTO granted patents and 2 published patent applications and 2 EPO patents. Top assignees: Adeia Semiconductor Bonding Technologies Inc., Google Inc., Adeia Semiconductor Technologies LLC. Active years: 2016-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Akash Agrawal. Retrieved from https://idiyas.com/inventor/akash-agrawal

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 16 

% Patents Active = 87.5

 

Average Co-Inventor Count = 5.6

ph-index = 3

Forward Citations = 87(Granted Patents)


Company Filing History:

goldMedal12 out of 1,909 
 
Adeia Semiconductor Bonding Technologies Inc.
 patents
silverMedal2 out of 33,959 
 
Google Inc.
 patents
bronzeMedal1 out of 32 
 
Adeia Semiconductor Technologies LLC
 patents
4. 1 out of 14,454 
 
Applied Materials, Inc.
 patents

Years Active: 2016-2026

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16 patents (USPTO):Explore Patents
1. RE51016 - Integrated circuit assemblies with rigid layers used for protection against mechanical thinning and for other purposes, and methods of fabricating such assemblies (2026-08-25),
2. 12711033 - EVALUATING NEW FEATURE(S) FOR CLIENT DEVICE(S) BASED ON PERFORMANCE MEASURE(S) (2026-08-18),
3. 12450518 - Evaluating on-device machine learning model(s) based on performance measures of client device(s) and/or the on-device machine learning model(s) (2025-10-21),
4. 12278172 - Substrate frame design for three-dimensional stacked electronic assemblies and method for the same (2025-04-14),
5. 10790222 - Bonding of laminates with electrical interconnects (2020-09-29),
6. 10354945 - Multi-surface edge pads for vertical mount packages and methods of making package stacks (2019-07-16),
7. 10283445 - Bonding of laminates with electrical interconnects (2019-05-07),
8. 10008469 - Wafer-level packaging using wire bond wires in place of a redistribution layer (2018-06-26),
9. 9859234 - Methods and structures to repair device warpage (2018-01-02),
10. 9847238 - Fan-out wafer-level packaging using metal foil lamination (2017-12-19),
11. 9824974 - Integrated circuit assemblies with rigid layers used for protection against mechanical thinning and for other purposes, and methods of fabricating such assemblies (2017-11-21),
12. 9728524 - Enhanced density assembly having microelectronic packages mounted at substantial angle to board (2017-08-08),
13. 9646946 - Fan-out wafer-level packaging using metal foil lamination (2017-05-09),
14. 9548273 - Integrated circuit assemblies with rigid layers used for protection against mechanical thinning and for other purposes, and methods of fabricating such assemblies (2017-01-17),
15. 9543277 - Wafer level packages with mechanically decoupled fan-in and fan-out areas (2017-01-10),

Title: The Innovative Journey of Akash Agrawal

Introduction: Akash Agrawal, a visionary inventor based in San Jose, CA, has made significant contributions to the field of technology through his groundbreaking innovations.

Latest Patents: Akash Agrawal holds several patents in the areas of artificial intelligence, machine learning, and renewable energy technologies, showcasing his versatility and forward-thinking approach.

Career Highlights: With a background in computer science and engineering, Akash Agrawal has worked for top tech companies in Silicon Valley, where he honed his skills and developed a passion for creating cutting-edge solutions.

Collaborations: Throughout his career, Akash Agrawal has collaborated with leading researchers, engineers, and scientists to bring his ideas to life, resulting in successful projects that have had a lasting impact on the industry.

Conclusion: Akash Agrawal's relentless pursuit of innovation and his commitment to pushing the boundaries of technology make him a true trailblazer in the world of inventions. His work continues to inspire and shape the future of technological advancements.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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