The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 19, 2017
Filed:
Feb. 27, 2017
Invensas Corporation, San Jose, CA (US);
Xuan Li, San Jose, CA (US);
Rajesh Katkar, San Jose, CA (US);
Long Huynh, Santa Clara, CA (US);
Laura Wills Mirkarimi, Sunol, CA (US);
Bongsub Lee, Mountain View, CA (US);
Gabriel Z. Guevara, San Jose, CA (US);
Tu Tam Vu, San Jose, CA (US);
Kyong-Mo Bang, Fremont, CA (US);
Akash Agrawal, San Jose, CA (US);
Invensas Corporation, San Jose, CA (US);
Abstract
Fan-out wafer-level packaging (WLP) using metal foil lamination is provided. An example wafer-level package incorporates a metal foil, such as copper (Cu), to relocate bonding pads in lieu of a conventional deposited or plated RDL. A polymer such as an epoxy layer adheres the metal foil to the package creating conductive contacts between the metal foil and metal pillars of a die. The metal foil may be patterned at different stages of a fabrication process. An example wafer-level package with metal foil provides relatively inexpensive electroplating-free traces that replace expensive RDL processes. Example techniques can reduce interfacial stress at fan-out areas to enhance package reliability, and enable smaller chips to be used. The metal foil provides improved fidelity of high frequency signals. The metal foil can be bonded to metallic pillar bumps before molding, resulting in less impact on the mold material.