The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2017

Filed:

Jun. 30, 2016
Applicant:

Invensas Corporation, San Jose, CA (US);

Inventors:

Min Tao, San Jose, CA (US);

Zhuowen Sun, Campbell, CA (US);

Hoki Kim, Santa Clara, CA (US);

Wael Zohni, San Jose, CA (US);

Akash Agrawal, San Jose, CA (US);

Assignee:

Invensas Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/49 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 25/10 (2006.01); H01L 25/065 (2006.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01); H05K 1/18 (2006.01); H05K 1/11 (2006.01);
U.S. Cl.
CPC ...
H01L 25/105 (2013.01); H01L 23/49805 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H05K 1/11 (2013.01); H05K 1/181 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06582 (2013.01); H01L 2225/06589 (2013.01); H05K 2201/10378 (2013.01);
Abstract

A microelectronic assembly includes a plurality of stacked microelectronic packages, each comprising a dielectric element having a major surface, an interconnect region adjacent an interconnect edge surface which extends away from the major surface, and plurality of package contacts at the interconnect region. A microelectronic element has a front surface with chip contacts thereon coupled to the package contacts, the front surface overlying and parallel to the major surface. The microelectronic packages are stacked with planes defined by the dielectric elements substantially parallel to one another, and the package contacts electrically coupled with panel contacts at a mounting surface of a circuit panel via an electrically conductive material, the planes defined by the dielectric elements being oriented at a substantial angle to the mounting surface.


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