Adeia Semiconductor Bonding Technologies Inc.

Google Inc.

Applied Materials, Inc.

Akash Agrawal

Rajesh Katkar

Bongsub Lee

Laura Wills Mirkarimi

Kyong-Mo Bang

Gabriel Z Guevara

Tu Tam Vu

Xuan Li

Long Huynh

Liang Wang

Cyprian Emeka Uzoh

Wael Zohni

Charles Gerard Woychik

Guilian Gao

Hong Shen

Arkalgud R Sitaram

Belgacem Haba

Javier A DeLaCruz

Willmar E Subido

Min Tao

Hoki Kim

Zhuowen Sun

Dragan Zivkovic

Françoise Beaufays

Scott P McGrath

Javier A Delacruz

Prashanth Ganeshbaabu

Tamar Lucassen

Implementations disclosed herein are directed to systems and methods for evaluating on-device machine learning (ML) model(s) based on performance measure(s) of client device(s) and/or the on-device ML model(s). The client device(s) can include on-device memory that stores the on-device ML model(s) and a plurality of testing instances for the on-device ML model(s). When certain condition(s) are satisfied, the client device(s) can process, using the on-device ML model(s), the plurality of testing instances to generate the performance measure(s). The performance measure(s) can include, for example, latency measure(s), memory consumption measure(s), CPU usage measure(s), ML model measure(s) (e.g., precision and/or recall), and/or other measures. In some implementations, the on-device ML model(s) can be activated (or kept active) for use locally at the client device(s) based on the performance measure(s). In other implementations, the on-device ML model(s) can be sparsified based on the performance measure(s).

Evaluating on-device machine learning model(s) based on performance measures of client device(s) and/or the on-device machine learning model(s)

In order to relieve the stress on the substrates in a 3D stacked electronic assembly, a substrate frame is divided into a plurality of frame sections that are separated by spaces between the frame sections. These separations allow the substrates to expand/contract in response to temperature variations and other environmental conditions, and generally allow the substrates to move in one or more axial directions. The separations between the substrate portions are design-specific for each substrate design. The placement of IC packages on either side of the substrate is analyzed to identify areas of maximal warpage through physical measurements, physical model simulations, or using a trained neural network. The spaces in the substrate frame are then be placed next to or aligned with the areas of maximal warpage to reduce the stress on the substrate.

Substrate frame design for three-dimensional stacked electronic assemblies and method for the same

A microelectronic assembly including first and second laminated microelectronic elements is provided. A patterned bonding layer is disposed on a face of each of the first and second laminated microelectronic elements. The patterned bonding layers are mechanically and electrically bonded to form the microelectronic assembly.

Bonding of laminates with electrical interconnects

Multi-surface edge pads for vertical mount packages and methods of making package stacks are provided. Example substrates for vertical surface mount to a motherboard have multi-surface edge pads. The vertical mount substrates may be those of a laminate-based FlipNAND. The multi-surface edge pads have cutouts or recesses that expose more surfaces and more surface area of the substrate for bonding with the motherboard. The cutouts in the edge pads allow more solder to be used between the attachment surface of the substrate and the motherboard. The placement and geometry of the resulting solder joint is stronger and has less internal stress than conventional solder joints for vertical mounting. In an example process, blind holes can be drilled into a thickness of a substrate, and the blind holes plated with metal. The substrate can be cut in half though the plated holes to provide two substrates with plated multi-surface edge pads including the cutouts for mounting to the motherboard.

Multi-surface edge pads for vertical mount packages and methods of making package stacks

An apparatus relates generally to a microelectronic package. In such an apparatus, a microelectronic die has a first surface, a second surface opposite the first surface, and a sidewall surface between the first and second surfaces. A plurality of wire bond wires with proximal ends thereof are coupled to either the first surface or the second surface of the microelectronic die with distal ends of the plurality of wire bond wires extending away from either the first surface or the second surface, respectively, of the microelectronic die. A portion of the plurality of wire bond wires extends outside a perimeter of the microelectronic die into a fan-out ('FO') region. A molding material covers the first surface, the sidewall surface, and portions of the plurality of the wire bond wires from the first surface of the microelectronic die to an outer surface of the molding material.

Wafer-level packaging using wire bond wires in place of a redistribution layer

A method of processing an interconnection element can include providing a substrate element having front and rear opposite surfaces and electrically conductive structure, a first dielectric layer overlying the front surface and a plurality of conductive contacts at a first surface of the first dielectric layer, and a second dielectric layer overlying the rear surface and having a conductive element at a second surface of the second dielectric layer. The method can also include removing a portion of the second dielectric layer so as to reduce the thickness of the portion, and to provide a raised portion of the second dielectric layer having a first thickness and a lowered portion having a second thickness. The first thickness can be greater than the second thickness. At least a portion of the conductive element can be recessed below a height of the first thickness of the second dielectric layer.

Methods and structures to repair device warpage

Fan-out wafer-level packaging (WLP) using metal foil lamination is provided. An example wafer-level package incorporates a metal foil, such as copper (Cu), to relocate bonding pads in lieu of a conventional deposited or plated RDL. A polymer such as an epoxy layer adheres the metal foil to the package creating conductive contacts between the metal foil and metal pillars of a die. The metal foil may be patterned at different stages of a fabrication process. An example wafer-level package with metal foil provides relatively inexpensive electroplating-free traces that replace expensive RDL processes. Example techniques can reduce interfacial stress at fan-out areas to enhance package reliability, and enable smaller chips to be used. The metal foil provides improved fidelity of high frequency signals. The metal foil can be bonded to metallic pillar bumps before molding, resulting in less impact on the mold material.

Fan-out wafer-level packaging using metal foil lamination

Die () and/or undiced wafers and/or multichip modules (MCMs) are attached on top of an interposer () or some other structure (e.g. another integrated circuit) and are covered by an encapsulant (). Then the interposer is thinned from below. Before encapsulation, a layer () more rigid than the encapsulant is formed on the interposer around the die to reduce or eliminate interposer dishing between the die when the interposer is thinned by a mechanical process (e.g. CMP). Other features are also provided.

Integrated circuit assemblies with rigid layers used for protection against mechanical thinning and for other purposes, and methods of fabricating such assemblies

A microelectronic assembly includes a plurality of stacked microelectronic packages, each comprising a dielectric element having a major surface, an interconnect region adjacent an interconnect edge surface which extends away from the major surface, and plurality of package contacts at the interconnect region. A microelectronic element has a front surface with chip contacts thereon coupled to the package contacts, the front surface overlying and parallel to the major surface. The microelectronic packages are stacked with planes defined by the dielectric elements substantially parallel to one another, and the package contacts electrically coupled with panel contacts at a mounting surface of a circuit panel via an electrically conductive material, the planes defined by the dielectric elements being oriented at a substantial angle to the mounting surface.

Enhanced density assembly having microelectronic packages mounted at substantial angle to board

A fan-out microelectronic package is provided in which bond wires electrically couple bond pads on a microelectronic element, e.g., a semiconductor chip which may have additional traces thereon, with contacts at a fan-out area of a dielectric element adjacent an edge surface of the chip. The bond wires mechanically decouple the microelectronic element from the fan-out area, which can make the electrical interconnections less prone to reliability issues due to effects of differential thermal expansion, such as caused by temperature excursions during initial package fabrication, bonding operations or thermal cycling. In addition, mechanical decoupling provided by the bond wires may also remedy other mechanical issues such as shock and possible delamination of package elements.

Wafer level packages with mechanically decoupled fan-in and fan-out areas

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San Jose, CA, United States of America

Akash Agrawal