The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 02, 2018
Filed:
Aug. 06, 2015
Invensas Corporation, San Jose, CA (US);
Cyprian Emeka Uzoh, San Jose, CA (US);
Guilian Gao, San Jose, CA (US);
Bongsub Lee, Mountain View, CA (US);
Scott McGrath, Scotts Valley, CA (US);
Hong Shen, Palo Alto, CA (US);
Charles G. Woychik, San Jose, CA (US);
Arkalgud R. Sitaram, Cupertino, CA (US);
Akash Agrawal, San Jose, CA (US);
Invensas Corporation, San Jose, CA (US);
Abstract
A method of processing an interconnection element can include providing a substrate element having front and rear opposite surfaces and electrically conductive structure, a first dielectric layer overlying the front surface and a plurality of conductive contacts at a first surface of the first dielectric layer, and a second dielectric layer overlying the rear surface and having a conductive element at a second surface of the second dielectric layer. The method can also include removing a portion of the second dielectric layer so as to reduce the thickness of the portion, and to provide a raised portion of the second dielectric layer having a first thickness and a lowered portion having a second thickness. The first thickness can be greater than the second thickness. At least a portion of the conductive element can be recessed below a height of the first thickness of the second dielectric layer.