Taipei, Taiwan

Yen Chuang

This inventor holds 13 USPTO granted patents and 9 published patent applications. Top assignees: Taiwan Semiconductor Manufacturing Comp. Ltd., National Taiwan University. Active years: 2006-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yen Chuang. Retrieved from https://idiyas.com/inventor/yen-chuang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 13 

% Patents Active = 69.2

Average Co-Inventor Count = 3.6

ph-index = 2

Forward Citations = 24(Granted Patents)


Location History:

  • Taipei, TW (2006 - 2024)
  • Kaohsiung, TW (2024)

Company Filing History:


Years Active: 2006-2026

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13 patents (USPTO):Explore Patents

Title: Yen Chuang - Innovator in Semiconductor Technology

Introduction

Yen Chuang is an innovative inventor based in Baoshan Township, Taiwan. She has made significant contributions to the field of semiconductor technology. Although she currently holds no granted patents, her work in developing advanced methods for transistor isolation is noteworthy.

Latest Patent Applications

Yen Chuang's latest patent application is titled "STACKED TRANSISTOR ISOLATION FEATURES AND METHODS OF FORMING THE SAME." This application outlines a method that includes patterning a lower semiconductor nanostructure, an upper semiconductor nanostructure, and a dummy nanostructure. The dummy nanostructure is disposed between the lower and upper semiconductor nanostructures and includes doped silicon. The method further describes forming an opening between the two semiconductor nanostructures by etching the doped silicon of the dummy nanostructure. An isolation structure is then formed in the opening, followed by the deposition of a gate dielectric around the isolation structure, the upper semiconductor nanostructure, and the lower semiconductor nanostructure.

Conclusion

Yen Chuang is a promising inventor in the semiconductor field, and her innovative approaches to transistor isolation may pave the way for future advancements.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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