The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Jan. 05, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Hsinchu, TW;

Inventors:

Miao-Syuan Fan, Hsinchu, TW;

Yen Chuang, Taipei, TW;

Yuan-Lin Lin, Hsinchu, TW;

Ta-Hsiang Kung, New Taipei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 10/00 (2026.01); H10D 84/83 (2025.01); H10P 14/60 (2026.01); H10P 14/69 (2026.01); H10P 14/692 (2026.01); H10P 30/40 (2026.01); H10P 50/28 (2026.01); H10W 10/17 (2026.01); H10P 95/00 (2026.01);
U.S. Cl.
CPC ...
H10W 10/014 (2026.01); H10D 84/834 (2025.01); H10P 14/6334 (2026.01); H10P 14/6905 (2026.01); H10P 14/6939 (2026.01); H10P 30/40 (2026.01); H10P 50/283 (2026.01); H10W 10/17 (2026.01); H10P 95/062 (2026.01);
Abstract

A method of manufacturing a semiconductor device includes: forming mutually parallel three-dimensional (3D) conductive channels coated with a conformal sacrificial layer, the 3D conductive channels coated with the conformal sacrificial layer being formed on a semiconductor substrate; depositing a dielectric material to fill spaces between the 3D conductive channels coated with the conformal sacrificial layer, wherein a portion or all of the deposited dielectric material is doped with boron, lithium, or beryllium; performing chemical mechanical polishing (CMP) to remove a top portion of the deposited dielectric material and to expose tops of the 3D conductive channels; and after the CMP, removing the conformal sacrificial layer coating the 3D conductive channels by etching to form 3D dielectric features spaced apart from the 3D conductive channels and comprising the deposited dielectric material.


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