Taiwan Semiconductor Manufacturing Comp. Ltd.

National Taiwan University

Yen Chuang

Chui-Ya Peng

Yuh-Ta Fan

Chih-Fen Chen

Pin-Hen Lin

Ching Yu

Min-Hao Hong

Vincent Chen

Pu-Fang Chen

Chih-Fu Chang

Yu-Jui Wu

Bone-Fong Wu

Jiun-Yun Li

Wei-Fan Lee

Chia-Yu Liu

Wei-Chih Hou

Yuan-feng Chao

Tse-En Chang

Chieh Chih Ting

Ming-Sen Chen

Shao Hua Wang

Nai-Wen Hsu

Hsiu-Yung Lin

The present disclosure describes a semiconductor device with a fill structure. The semiconductor structure includes first and second fin structures on a substrate, an isolation region on the substrate and between the first and second fin structures, a first gate structure disposed on the first fin structure and the isolation region, a second gate structure disposed on the second fin structure and the isolation region, and the fill structure on the isolation region and between the first and second gate structures. The fill structure includes a dielectric structure between the first and second gate structures and an air gap enclosed by the dielectric structure. The air gap is below top surfaces of the first and second fin structures.

Fill structures with air gaps

A flash memory device includes a substrate, a semiconductor quantum well layer, a semiconductor spacer, a semiconductor channel layer, a gate structure, and source/drain regions. The semiconductor quantum well layer is formed of a first semiconductor material and is disposed over the substrate. The semiconductor spacer is formed of a second semiconductor material and is disposed over the first semiconductor channel layer. The semiconductor channel layer is formed of the first semiconductor material and is disposed over the semiconductor spacer. Thea gate structure is over the second semiconductor channel layer. The source/drain regions are over the substrate and are on opposite sides of the gate structure.

Flash memory device and method thereof

A semiconductor device includes a gate stack over a semiconductor substrate. A spacer extends along a first sidewall of the gate stack. An epitaxy structure is in the semiconductor substrate. A liner wraps around the epitaxy structure and has an outer surface in contact with the semiconductor substrate and an inner surface facing the epitaxy structure. The outer surface of the liner has a first facet extending upwards and towards the gate stack from a bottom of the first liner and a second facet extending upwards and towards an outer sidewall of the spacer from a top of the first facet to a top of the liner, such that a corner is formed between the first facet and the second facet, and the inner surface of the first liner defines a first curved corner pointing towards the corner formed between the first facet and the second facet.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a gate stack over a semiconductor substrate. A spacer extends substantially along a first sidewall of the gate stack. An epitaxy structure is in the semiconductor substrate. A liner wraps around the epitaxy structure and has an outer surface in contact with the semiconductor substrate and an inner surface facing the epitaxy structure. The outer surface of the liner has a first facet extending upwards and towards the gate stack from a bottom of the first liner and a second facet extending upwards and towards an outer sidewall of the spacer from a top of the first facet to a top of the liner, such that a corner is formed between the first facet and the second facet, and the inner surface of the first liner defines a first curved corner pointing towards the corner formed between the first facet and the second facet.

Semiconductor device

A semiconductor device includes a substrate, a liner, and an epitaxy structure. The substrate has a recess. The liner is disposed in the recess. The liner is denser than the substrate. The epitaxy structure is disposed in the recess. The liner is disposed between the epitaxy structure and the substrate.

One or more semiconductor arrangements are provided. The semiconductor arrangements include a buried layer over a well, a dielectric layer over the buried layer, a first gate stack over the dielectric layer and a S/D region disposed proximate the first gate stack. The S/D region has a first tip proximity region that extends under the first gate stack. One or more methods of forming a semiconductor arrangement are also provided. The methods include forming a S/D recess in at least one of a dielectric layer, a buried layer or a well, wherein the S/D recess is proximate a first gate stack and has a first recess tip proximity region that extends under the first gate stack as a function of the buried layer, and forming a S/D region in the S/D recess such that the S/D region has a first tip proximity region that extends under the first gate stack.

Semiconductor arrangement with stress control and method of making

A method of forming a dopant implant region in a MOS transistor device having a dopant profile having a target dopant concentration includes implanting a first concentration of dopants into a region of a substrate, where the first concentration of dopants is less than the target dopant concentration, and without annealing the substrate after the implanting step, performing at least one second implanting step to implant at least one second concentration of dopants into the region of the substrate to bring the dopant concentration in the region to the target dopant concentration.

Dopant implantation method using multi-step implants

A method of predicting CMP removal rate for CMP process in a CMP process tool. The method predicts CMP removal rates for CMP processes without polishing additional control wafers. The CMP process performed by the CMP process tool can be easily transferred accordingly, such that uptime of the CMP process tool is increased. In addition, number of control wafers used and production costs are also reduced.

Method of predicting CMP removal rate for CMP process in a CMP process tool in order to determine a required polishing time

A method for polishing a material layer on a semiconductor wafer to a desired target layer thickness. The method includes calculating a compensated removal rate based on the thickness of material to be removed from a material layer on the wafer according to a standard value; the current material removal rate of the CMP apparatus; and the offset thickness, which equals the difference between the thickness of the material layer which would be attained using the current material removal rate and the target thickness for the material layer. The calculated compensated removal rate is then programmed into the controller for the CMP apparatus, which polishes the material layer at the calculated compensated removal rate to achieve the desired target layer thickness for the layer.

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Taipei, Taiwan

Yen Chuang