Tsong-Hua Ou

This inventor holds 40 USPTO granted patents and 1 published patent application, primarily in Integrated Circuit Design. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2010-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Tsong-Hua Ou. Retrieved from https://idiyas.com/inventor/tsong-hua-ou

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 40 (Patent Applications = 1)

% Patents Active = 52.5

Average Co-Inventor Count = 6.5

ph-index = 9

Forward Citations = 197(Granted Patents)

Company Filing History:

40 out of 42,810

Taiwan Semiconductor Manufacturing Comp. Ltd.

patents

Years Active: 2010-2025

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Areas of Expertise:

Integrated Circuit Design

Conductive Patterns

Self-Aligned Interconnects

Multiple Edge Enabled Patterning

FinFETs

Photoresist Mask Patterns

Double Patterning

Thermal Design

Optical Proximity Correction

Pattern Density Optimization

DFM Analysis

Electrical Parameter Extraction

40 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 12438000 - Methods for integrated circuit design and fabrication (2025-10-07),

2. 12013643 - Method of cutting conductive patterns (2024-06-18),

3. 11429028 - Method of cutting conductive patterns (2022-08-30),

4. 10930505 - Methods for integrated circuit design and fabrication (2021-02-23),

5. 10509322 - Method of cutting conductive patterns (2019-12-17),

6. 10410863 - Methods for integrated circuit design and fabrication (2019-09-10),

7. 9852908 - Methods for integrated circuit design and fabrication (2017-12-26),

8. 9754881 - Designed-based interconnect structure in semiconductor structure (2017-09-05),

9. 9627310 - Semiconductor device with self-aligned interconnects (2017-04-18),

10. 9524939 - Multiple edge enabled patterning (2016-12-20),

11. 9478540 - Adaptive fin design for FinFETs (2016-10-25),

12. 9390223 - Method of determining whether a layout is colorable (2016-07-12),

13. 9380709 - Method of cutting conductive patterns (2016-06-28),

14. 9362119 - Methods for integrated circuit design and fabrication (2016-06-07),

15. 9287125 - Multiple edge enabled patterning (2016-03-15),

Title: Tsong-Hua Ou: Pioneering Inventor Shaping the Future of Technology in Taipei

Introduction:

Tsong-Hua Ou's passion for innovation and his unwavering drive to make a difference have positioned him as a pioneering inventor in Taipei, Taiwan, and beyond. With a portfolio of 38 patents, his dedication to pushing boundaries in technology continues to inspire future generations of inventors.

Latest Patents:

1. Method of cutting conductive patterns: Ou's innovative method involves providing a first layout of a layer with metal patterns and utilizing a cut mask to remove material from different regions, resulting in distinct metal patterns.

2. Methods for integrated circuit design and fabrication: His method includes forming spacer features and conducting photolithographic patterning processes to create intricate semiconductor structures.

Career Highlights:

Tsong-Hua Ou is a notable figure at Taiwan Semiconductor Manufacturing Company Ltd., where his expertise and creativity have led to groundbreaking advancements in semiconductor technology. His work has significantly impacted the industry and set new standards for innovation.

Collaborations:

Alongside accomplished coworkers Ru-Gun Liu and Wen-Chun Huang, Ou has collaborated on various projects, combining their collective knowledge and skills to tackle complex technological challenges. Their teamwork has resulted in the development of cutting-edge solutions that have further solidified Ou's reputation as a leader in the field.

Conclusion:

Inventor Tsong-Hua Ou's remarkable journey as a pioneering inventor in Taipei, Taiwan, reflects his commitment to innovation and excellence in technology. His transformative contributions and collaborations serve as a testament to his visionary approach and enduring legacy in the world of inventions and patents.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

1 patent pending: