Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsong-Hua Ou

Ru-Gun Liu

Wen-Chun Huang

Ken-Hsien Hsieh

Ying-Chou Cheng

Chih-Ming Lai

Shih-Ming Chang

Tsai-Sheng Gau

Huang-Yu Chen

Yao-Ching Ku

Chin-Hsiung Hsu

Yu-Po Tang

Boren Luo

Wen-Hao Liu

Yi-Kan Cheng

Ming-Feng Shieh

Wen-Hao Chen

Wen-Li Cheng

Min-Hong Wu

Li-Chun Tien

Burn Jeng Lin

Yuan-Te Hou

Ya Hui Chang

Kuei Shun Chen

Hsiao-Shu Chao

Ming-Hui Chih

Te-Chih Huang

Chih-Yang Yeh

Chia-Ping Chiang

Cheng Kun Tsai

Fang-Yu Fan

Cheng-Lung Tsai

Yu Lun Liu

Shu-Chen Lu

Chih-Wei Hsu

Chih-Liang Chen

Charles Chew-Yuen Young

Kam-Tou Sio

Chun-Kuang Chen

Yung-Sung Yen

Pin-Dai Sue

Yung-Chin Hou

George Liu

Cliff Hou

Chung-Kai Lin

Yih-Yuh Doong

Shu-Hui Sung

Shu-Min Chen

Ping-Heng Yeh

Josh J H Feng

Lee-Chung Lu

Wen-Ju Preet Yang

Chin-Chang Hsu

Ting Yu Chen

Chia-Chu Liu

Ching Fu Chang

Tzu-Chin Lin

Chia-Chi Lin

Hung Lung Lin

Jen-Chieh Lo

Chien Lin Ho

Luke Lo

Jhih-Jian Wang

The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.

Methods for integrated circuit design and fabrication

A method includes: providing a first layout of a first layer over a substrate, the first layer having at least one metal pattern, and generating a second layout by placing a cut mask at a first position relative to the substrate to remove material from a first region of the at least one metal pattern to provide a first metal pattern and placing the cut mask at a second position relative to the first layer over the substrate to remove material from a second region of the at least one metal pattern to provide a second metal pattern.

Method of cutting conductive patterns

A method includes patterning a layer over a substrate with a first metal pattern; using a cut mask in a first position relative to the substrate to perform a first cut patterning for removing material from a first region within the first pattern; and using the same cut mask to perform a second cut patterning while in a second position relative to the same layer over the substrate, for removing material from a second region in a second metal pattern of the same layer over the substrate.

The present disclosure provides a method that includes forming a first pattern feature and a second pattern feature over a material layer by a first photolithographic process. The method also includes forming a first spacer feature on a sidewall of the first pattern feature and a second spacer feature on a sidewall of the second pattern feature. Additionally, the method includes forming a third pattern feature on the material layer between the first spacer feature and the second spacer feature by a second photolithographic process. In addition, the method includes removing the first and second spacer features to expose a portion of the material layer.

Semiconductor structures are provided. The semiconductor structure includes a plurality of gate structures extending in a first direction formed over a substrate. The gate structures follow the following equation:  Pis the minimum value among gate pitches of the gate structures, and Lis the minimum value among gate lengths of the gate structures. His the minimum value among gate heights of the gate structures.

Designed-based interconnect structure in semiconductor structure

A multilayer device and method for fabricating a multilayer device is disclosed. An exemplary multilayer device includes a substrate, a first interlayer dielectric (ILD) layer disposed over the substrate, and a first conductive layer including a first plurality of conductive lines formed in the first ILD layer. The device further includes a second ILD layer disposed over the first ILD layer, and a second conductive layer including a second plurality of conductive lines formed in the second ILD layer. At least one conductive line of the second plurality of conductive lines is formed adjacent to at least one conductive line of the first plurality of conductive lines. The at least one conductive line of the second plurality of conductive lines contacts the at least one conductive line of the first plurality of conductive lines at an interface.

Semiconductor device with self-aligned interconnects

Provided is an alignment mark having a plurality of sub-resolution elements. The sub-resolution elements each have a dimension that is less than a minimum resolution that can be detected by an alignment signal used in an alignment process. Also provided is a semiconductor wafer having first, second, and third patterns formed thereon. The first and second patterns extend in a first direction, and the third pattern extend in a second direction perpendicular to the first direction. The second pattern is separated from the first pattern by a first distance measured in the second direction. The third pattern is separated from the first pattern by a second distance measured in the first direction. The third pattern is separated from the second pattern by a third distance measured in the first direction. The first distance is approximately equal to the third distance. The second distance is less than twice the first distance.

Multiple edge enabled patterning

A method of designing a standard cell includes determining a minimum fin pitch of semiconductor fins in the standard cell, wherein the semiconductor fins are portions of FinFETs; and determining a minimum metal pitch of metal lines in a bottom metal layer over the standard cell, wherein the minimum metal pitch is greater than the minimum fin pitch. The standard cell is placed in an integrated circuit and implemented on a semiconductor wafer.

Adaptive fin design for FinFETs

A method of determining whether a layout is colorable includes assigning nodes to polygon features of the layout. The method includes designating nodes as being adjacent nodes for nodes separated by less than a minimum pitch. The method includes iteratively removing nodes having less than three adjacent nodes from consideration to identify a node arrangement, wherein all nodes in the node arrangement have at least three adjacent nodes. The method includes determining whether the layout is colorable based on the node arrangement. Determining whether the layout is colorable includes independently assessing each internal node of node arrangement to determine whether each internal node of the node arrangement is colorable. The method includes generating a colored layout design for fabrication of the semiconductor device if each internal node of the node arrangement is colorable; and modifying the layout if at least one internal node of the node arrangement is not colorable.

Method of determining whether a layout is colorable

The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of: forming a plurality of first features over the target material layer using a first sub-layout, with each first feature having sidewalls; forming a plurality of spacer features, with each spacer feature conforming to the sidewalls of one of the first features and having a spacer width; and forming a plurality of second features over the target material layer using a second sub-layout. The method further includes steps of removing the plurality of spacer features from around each first feature and patterning the target material layer using the plurality of first features and the plurality of second features. Other methods and associated patterned semiconductor wafers are also provided herein.

Growing community of inventors

Taipei, Taiwan

Tsong-Hua Ou