Kawasaki, Japan

Takao Yonehara

This inventor holds 192 USPTO granted patents and 2 published patent applications, plus 1 CIPO patent and 2 EPO patents, primarily in Porous Semiconductor Manufacturing (CPC class 437 83). Top assignees: Canon Kabushiki Kaisha, Solexel, Inc., Leland Stanford Junior University. Active years: 1989-2020.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Takao Yonehara. Retrieved from https://idiyas.com/inventor/takao-yonehara

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 192 

% Patents Active = 75.5


 

Average Co-Inventor Count = 2.5

ph-index = 47

Forward Citations = 8,597(Granted Patents)

Forward Citations (Not Self Cited) = 7,977(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Shimomaruko, Ohta-ku, Tokyo, JP (1996)
  • Kanagawa-ken, JP (2003 - 2009)
  • Atsugi, JP (1989 - 2014)
  • Kawasaki, JP (2007 - 2014)
  • Kanagawa, JP (1996 - 2015)
  • Sunnyvale, CA (US) (2013 - 2018)
  • Milpitas, CA (US) (2012 - 2020)

Company Filing History:


Years Active: 1989-2020

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Areas of Expertise:
Porous Semiconductor
Laser Splitting
LED Array
High-Throughput Equipment
Silicon Manufacturing
Semiconductor Device
Gallium Nitride
Image Sensing
Substrate Structure
Field-Effect Transistor
Optical Transmittance
Microelectronics
192 patents (USPTO):Explore Patents

Title: Takao Yonehara: Innovative Mind in Semiconductor Fabrication

Introduction:

Takao Yonehara, a prolific inventor hailing from Kawasaki, Japan, has made significant contributions to the field of semiconductor fabrication. With a remarkable number of 192 patents under his belt, Yonehara has played a vital role in advancing the development of porous semiconductor layers, particularly in applications such as photovoltaics, MEMS, and optoelectronics.

Latest Patents:

Yonehara's recent patented inventions include "Apparatus and methods for uniformly forming porous semiconductor on a substrate" and "High-throughput batch porous silicon manufacturing equipment design and processing methods." These patents focus on enabling high-productivity fabrication of uniform porous semiconductor layers, both single-layer and multi-layer structures.

The disclosed methods offer controlled and uniform fabrication of porous semiconductor layers, such as porous silicon, featuring either single or multiple porosity layers. These innovations find applications in various areas, ranging from MEMS separations and sacrificial layers for die detachment to MEMS device fabrication, membrane formation, and shallow trench isolation (STI) porous silicon. Additionally, Yonehara's inventions can be integrated with semiconductor microelectronics chips and optoelectronics, significantly enhancing their capabilities.

Career Highlights:

Throughout his career, Yonehara has worked with notable companies, including Canon Kabushiki Kaisha and Solexel, Inc. He has consistently demonstrated a deep understanding of semiconductor technologies and has been instrumental in driving advancements in production efficiency, quality, and performance.

Collaborations:

Yonehara has collaborated closely with talented individuals in his field. Notable coworkers include Kiyofumi Sakaguchi and Kenji Yamagata. These collaborations have resulted in a synergistic exchange of ideas and expertise, further enhancing the innovative potential of the teams involved.

Conclusion:

Takao Yonehara's contributions to the field of semiconductor fabrication have undoubtedly been substantial. Through his numerous patents and innovative approaches, he has paved the way for improved manufacturing processes and performance capabilities in various industries. Yonehara's expertise and dedication to advancing semiconductor technologies continue to make a significant impact, ensuring a brighter future for the field and its potential applications.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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