The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 26, 2016

Filed:

Jul. 20, 2012
Applicants:

Mehrdad M. Moslehi, Los Altos, CA (US);

Karl-josef Kramer, San Jose, CA (US);

David Xuan-qi Wang, Fremont, CA (US);

Pawan Kapur, Palo Alto, CA (US);

Somnath Nag, Saratoga, CA (US);

George D. Kamian, Scotts Valley, CA (US);

Jay Ashjaee, Milpitas, CA (US);

Takao Yonehara, Milpitas, CA (US);

Inventors:

Mehrdad M. Moslehi, Los Altos, CA (US);

Karl-Josef Kramer, San Jose, CA (US);

David Xuan-Qi Wang, Fremont, CA (US);

Pawan Kapur, Palo Alto, CA (US);

Somnath Nag, Saratoga, CA (US);

George D. Kamian, Scotts Valley, CA (US);

Jay Ashjaee, Milpitas, CA (US);

Takao Yonehara, Milpitas, CA (US);

Assignee:

Solexel, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/20 (2006.01); H01L 31/18 (2006.01);
U.S. Cl.
CPC ...
H01L 21/20 (2013.01); H01L 31/1804 (2013.01); Y02E 10/547 (2013.01); Y02P 70/521 (2015.11);
Abstract

An apparatus for forming porous silicon layers on at least two surfaces of a plurality of silicon templates in a batch electrochemical anodic etch process is provided. The apparatus comprises a plurality of edge-sealing template mounts operable to prevent formation of porous silicon at the edges of a plurality of templates. An electrolyte is disposed among the plurality of templates. The apparatus further comprises a power supply operable to switch polarity, change current intensity, and control etching time to produce the porous silicon layers.


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