The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 28, 2014

Filed:

Apr. 02, 2010
Applicants:

Takao Yonehara, Atsugi, JP;

Kiyofumi Sakaguchi, Mobara, JP;

Nobuo Kawase, Yokohama, JP;

Kenji Nakagawa, Isehara, JP;

Inventors:

Takao Yonehara, Atsugi, JP;

Kiyofumi Sakaguchi, Mobara, JP;

Nobuo Kawase, Yokohama, JP;

Kenji Nakagawa, Isehara, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/50 (2006.01); H01L 21/683 (2006.01); H01L 25/065 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 2225/06541 (2013.01); H01L 2221/68318 (2013.01); H01L 2225/06513 (2013.01); H01L 2221/6835 (2013.01); H01L 21/6835 (2013.01); H01L 2225/06548 (2013.01); H01L 2924/30105 (2013.01); H01L 2924/3025 (2013.01); H01L 24/94 (2013.01); H01L 2224/16145 (2013.01);
Abstract

A method of manufacturing a semiconductor chip including an integrated circuit and a through-electrode penetrating a semiconductor layer includes the steps of preparing a first substrate including a release layer and a semiconductor layer formed on the release layer; forming an integrated circuit in the semiconductor layer; forming, in the semiconductor layer, a hole or groove having a depth that does not reach the release layer; filling the hole or the groove with an electrical conductor; bonding a second substrate to the semiconductor layer to form a bonded structure; separating the bonded structure at the release layer to prepare the second substrate to which the semiconductor layer is transferred; and removing at least a portion of the reverse surface side of the semiconductor layer exposed by the separation to expose the bottom of the electrical conductor.


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