The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 13, 2018
Filed:
Dec. 08, 2014
Trutag Technologies, Inc., Kapolei, HI (US);
Karl-Josef Kramer, San Jose, CA (US);
Mehrdad M. Moslehi, Los Altos, CA (US);
Subramanian Tamilmani, San Jose, CA (US);
George D. Kamian, Scotts Valley, CA (US);
Jay Ashjaee, Cupertino, CA (US);
Takao Yonehara, Milpitas, CA (US);
TruTag Technologies, Inc., Kapolei, HI (US);
Abstract
This disclosure enables high-productivity controlled fabrication of uniform porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.