Sivagnanam Parthasarathy

Carlsbad, CA, United States of America

Sivagnanam Parthasarathy

This inventor holds 253 USPTO granted patents and 61 published patent applications and 4 EPO patents, primarily in Memory Device Technology (CPC class G11C16-26). Top assignees: Micron Technology Incorporated, Stmicroelectronics Gmbh, Edgestream, Inc.. Active years: 2003-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Sivagnanam Parthasarathy. Retrieved from https://idiyas.com/inventor/sivagnanam-parthasarathy

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 253 

% Patents Active = 89.3

 

Average Co-Inventor Count = 3.6

ph-index = 11

Forward Citations = 611(Granted Patents)

Forward Citations (Not Self Cited) = 365(Dec 10, 2025)


Inventors with similar research interests:

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Location History:

  • San Diego, CA (US) (2009)
  • Carlsbad, CA (US) (2003 - 2024)

Company Filing History:


Years Active: 2003-2026

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Areas of Expertise:
Error Correction
Voltage Calibration
Soft Bits
Charge Coupling
Memory Cells
Bit Flipping
Metadata Characterization
Dynamic Adjustment
Data Retrieval
NAND
Read Voltage
Error Handling
253 patents (USPTO):Explore Patents

Title: Sivagnanam Parthasarathy: Pioneering Innovator with 158 Patents

Introduction:

In the realm of technological advancements, certain individuals stand out for their exceptional contributions. Sivagnanam Parthasarathy, hailing from Carlsbad, CA, is one such innovator. With an impressive portfolio consisting of 158 patents, Parthasarathy has left an indelible mark on the field of memory systems. Let's delve into his latest patents, career highlights, and noteworthy collaborations to gain a deeper understanding of his expertise and accomplishments.

Latest Patents:

Among Parthasarathy's remarkable patents is "Self Adapting Iterative Read Calibration to Retrieve Data from Memory Cells." This cutting-edge memory subsystem focuses on iterative calibration of read voltages, enabling efficient retrieval of data from memory cells by calibrating higher read voltages based on the calibration results of lower read voltages. This innovation has the potential to optimize memory systems and enhance data retrieval processes significantly.

Another notable recent patent is "Iterative Error Correction with Adjustable Parameters after a Threshold Number of Iterations." This patent showcases Parthasarathy's prowess in processing devices within memory systems. By implementing an iterative low-density parity check (LDPC) correction process and adjusting certain criteria after a threshold number of iterations, this invention improves the error correction capabilities of memory systems, ensuring accurate retrieval of data.

Career Highlights:

Parthasarathy has demonstrated his technical brilliance while working with influential companies such as Micron Technology Incorporated and STMicroelectronics GmbH. His contributions to these organizations have helped shape the memory systems landscape and push the boundaries of technological innovation.

Collaborations:

Within the industry, Parthasarathy has had the privilege of collaborating with esteemed individuals. Notably, he has worked alongside Patrick Robert Khayat and Mustafa Nazmi Kaynak, both renowned for their expertise in the field. These collaborations have led to the combined intellect and creativity necessary to develop groundbreaking solutions.

Conclusion:

Sivagnanam Parthasarathy's significant contributions to the world of memory systems, as evidenced by his vast patent portfolio, showcases his immense talent and dedication to innovation. His latest patents, including self-adapting iterative read calibration and iterative error correction, highlight his ability to tackle complex challenges and enhance the efficiency of memory systems. As a respected figure in the industry, his collaborations with notable colleagues further evidence his commitment to driving technological advancements. Parthasarathy's invaluable contributions position him as a true pioneer in the field, and his work continues to shape the landscape of innovations and patents in memory systems.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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