Micron Technology Incorporated

Stmicroelectronics Gmbh

Stmicroelectronics S.r.l.

Stmicroelectronics S.a.

Edgestream, Inc.

Sivagnanam Parthasarathy

Mustafa Nazmi Kaynak

Patrick Robert Khayat

James Fitzpatrick

Kishore Kumar Muchherla

Sampath K Ratnam

Peter Sean Feeley

Shane G Nowell

Abdelhakim Alhussien

Vamsi Pavan Rayaprolu

Jiangang Wu

AbdelHakim S Alhussien

Eyal En Gad

Xiangang Luo

Devin M Batutis

Karl David Schuh

Nicholas Julian Richardson

Zhengang Chen

Qisong Lin

Renato C Padilla

Yoav Weinberg

Jung Sheng Hoei

Aswin Thiruvengadam

Saeed Sharifi Tehrani

Violante Moschiano

Jeffrey S McNeil, Jr

Robert B Eisenhuth

Shayan Srinivasa Garani

Mark Alan Helm

Akira Goda

William Henry Radke

Sean Stephen Eilert

Ameen D Akel

Dmitri A Yudanov

Steven Michael Kientz

Dung Viet Nguyen

Phong Sy Nguyen

Alessandro Risso

Shivasankar Gunasekaran

Daniel G Scobee

Frederick Jensen

Luca De Santis

Zhenlei Shen

Terry M Grunzke

Walter Di Francesco

Ali Mohammadzadeh

Lun Bin Huang

Gianfranco Valeri

Vamshi K Indavarapu

Lucia Botticchio

Jonathan Scott Parry

Aaron S Yip

Eric N Lee

Sundararajan Sankaranarayanan

Xinde Hu

Jeremy Binfet

Ugo Russo

Alexander Driker

Shantilal Doru

Ka Leung Ling

Sudha Thipparthi

Shao Chun Shi

Ashutosh Malshe

Huai-Yuan Tseng

Richard David Barndt

Preston Allen Thomson

Anthony Dwayne Weathers

Niccolo' Righetti

Andrew Cofler

Randall M Chung

Stefano Valle

Dillip Kumar Dash

Niccolo′ Righetti

Sead Zildzic

Aniryudh Reddy Durgam

Maged Bishay

Michael Zelevinsky

Lionel Chaverot

Shayan Garani Srinivasa

Embodiments disclosed can include selecting a target read window budget (RWB) increase and identifying a set of aggressor memory cells. They can also include generating a list of programming level states for the set of aggressor memory cells and identifying, in the list, an entry associated with a maximum RWB increase that is greater than or equal to the target RWB increase. They can further include responsive to identifying the entry with the total number of bits associated with a maximum RWB increase that is greater than or equal to the target RWB increase, modifying a parameter of the memory access operation with the adjustment associated with the identified entry.

Managing compensation for charge coupling and lateral migration in memory devices

An amount of voltage shift is determined for one or more memory cells of a block family based on an initial reference value pertaining to the one or more memory cells and a subsequent reference value pertaining to the one or more memory cells. The block family is associated with a first voltage bin or a second voltage bin based on the determined amount of voltage shift. The first voltage bin is associated with a first voltage offset and the second voltage bin is associated with a second voltage offset.

Voltage bin calibration based on a voltage distribution reference voltage

Described are systems and methods for validating read level voltage in memory devices. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines; and a controller coupled to the memory array, the controller to perform operations comprising: causing a read level voltage to be applied to a specified wordline of the plurality of wordlines; receiving an actual bit count reflecting a number of memory cells that have their respective threshold voltages below the read level voltage; and responsive to determining that a difference of an expected bit count and the actual bit count exceeds a predetermined threshold value, adjusting the read level voltage.

Validating read level voltage in memory devices

A memory device to manage the assignment of offset voltages for read operations, and to adjust read voltages using the offset voltages. The offset voltages are dynamically adjusted by a controller during operation of the memory device in response to read errors. In one approach, a first bin of offset voltages is assigned to a first region of a storage media. The first offset voltages are used to adjust read voltages for reading a page of first memory cells in the first region. The controller determines that at least one error has occurred in reading the page. In response to determining the error, the controller determines second offset voltages that can be used to read the first memory cell without causing a read error. Based on the second offset voltages, the controller identifies third offset voltages for assigning to the first region. The third offset voltages are used for adjusting read voltages for subsequent reads of pages in the first region. The third offset voltages can be assigned from an existing offset voltage bin, or a new offset voltage bin can be generated for the assignment.

Dynamic adjustment of offset voltages for reading memory cells in a memory device

Methods, systems, and apparatuses detect and mitigate a stall condition in an iterative bit flipping decoder. A codeword is received and one or more of the bits in the codeword are flipped in each of multiple iterations of bit flipping decoding using a first set of bit flipping rules. Each of the iterations includes a determination of a syndrome weight. In response to determining a count of iterations in which the syndrome weight increased satisfies a threshold, one or more of the bits in the codeword are flipped in a subsequent iteration using a second set of bit flipping rules that differs from the first set of bit flipping rules.

Detecting a stall condition in bit flipping decoding using syndrome weight slope

A method includes performing a read operation of a first codeword including first hard data and generating an error vector using a reliability metric of the first hard data. The first hard data and error vector are stored in first and second portions of memory. A first corrected codeword is returned that combines the error vector and the hard data from the first and second portions of memory. A read operation of a second codeword is performed, including second hard data and soft information. The hard data and soft information are stored in the first and second portions of memory. A bit of second hard data is flipped responsive to comparing a reliability metric of the bit of the second hard data to a bit flipping threshold, wherein flipping the bit includes updating the second hard data. The updated second codeword is returned resulting from reading the portions of memory.

Efficient memory use to support soft information in bit flipping decoders

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a data integrity check on a source set of memory cells, configured to store a first number of bits per memory cell, to obtain a data integrity metric value; responsive to determining that the data integrity metric value satisfies the threshold criterion, performing an error handling operation on the data stored on the source set of memory cells to generate corrected data; and causing the memory device to copy data the corrected data to a destination set of memory cells of the memory device, wherein the destination set of memory cells are configured to store a second number of bits per memory cell, wherein the second number of bits per memory cells is greater than the first number of bits per memory cell.

Memory compaction management in memory devices

Methods, apparatuses, and systems for in-or near-memory processing are described. Strings of bits (e.g., vectors) may be fetched and processed in logic of a memory device without involving a separate processing unit. Operations (e.g., arithmetic operations) may be performed on numbers stored in a bit-parallel way during a single sequence of clock cycles. Arithmetic may thus be performed in a single pass as numbers are bits of two or more strings of bits are fetched and without intermediate storage of the numbers. Vectors may be fetched (e.g., identified, transmitted, received) from one or more bit lines. Registers of a memory array may be used to write (e.g., store or temporarily store) results or ancillary bits (e.g., carry bits or carry flags) that facilitate arithmetic operations. Circuitry near, adjacent, or under the memory array may employ XOR or AND (or other) logic to fetch, organize, or operate on the data.

Methods for performing processing-in-memory operations, and related systems

A method includes determining, by a processing device, a value of a memory endurance state metric associated with a segment of a memory device in a memory sub-system; determining a target value of a code rate based on the value of the memory endurance state metric, and adjusting the code rate of the memory device according to the target value, wherein the code rate reflects a ratio of a number of memory units designated for storing host-originated data to a total number of memory units designated for storing the host-originated data and error correction metadata.

Adjustment of code rate as function of memory endurance state metric

A bit flipping decoder receives a codeword stored in a memory device. The bit flipping decoder determines a plurality of energy function values for the codeword and a least reliable of the energy function values for the codeword. In response to the bit flipping decoder determining the least reliable energy function value fails to satisfy a bit flipping criterion of a current iteration, the bit flipping decoder increments an iteration count. The incrementing of the iteration count bypasses a comparison of the plurality of energy function values with the bit flipping criterion of the current iteration.

Bypassing iterations in a bit flipping decoder using a least reliable bit energy function

A system can include a memory device and a processing device, operatively coupled with the memory device, to perform operations including reading a first copy of data stored in a first set of memory cells comprising a first memory cell, determining whether a threshold voltage of the first memory cell is within a first range of threshold voltages, responsive to determining that the threshold voltage of the first memory cell is within the first range of threshold voltages, reading a second copy of the data stored in a second set of memory cells comprising a second memory cell, determining whether a threshold voltage of the second memory cell is within a second range of threshold voltages, and responsive to determining that the threshold voltage of the second memory cell is outside the second range, using the second copy of the data.

Using duplicate data for improving error correction capability

A of bit flipping (BF) decoder decodes codewords using a first set of BF thresholds. A first minimum number of iterations of decoding performed on the codewords is determined to achieve a first target decoding rate. Codewords are decoded using a second set of BF thresholds. The first set of BF thresholds are more likely to cause bit flips than the second set of BF thresholds. A second minimum number of iterations of decoding performed on the codewords is determined to achieve a second target decoding rate. Bits in a codeword are flipped using the first set of BF thresholds for the first minimum number of iterations. Bits are flipped in the codeword using the second set of BF thresholds in response to determining the codeword remains undecoded as a result of the first minimum number of iterations.

Bit flipping decoder with optimized maximum iterations for varied bit flipping thresholds

A processing device in a memory sub-system determines a syndrome weight for a sense word read from a memory device and determines whether the syndrome weight for the sense word satisfies a threshold criterion. Responsive to the syndrome weight for the sense word satisfying a respective threshold criterion associated with a next iteration of a first decoding operation, bypassing the first decoding operation and initiating a second decoding operation for the sense word, wherein the second decoding operation has a higher error correction capability than the first decoding operation.

Early stopping of bit-flip low density parity check decoding based on syndrome weight

A memory system configured to dynamically adjust the amount of redundant information stored in memory cells of a wordline on an integrated circuit die based on a bit error rate. For example, in response to a determination that a bit error rate of the wordline is above a threshold, the memory system can store first data items as independent first codewords of an error correction code technique into a first portion of the memory cells of the wordline, generate second data items as redundant information from the first codewords, and store the second data items in a second portion of the memory cells of the wordline. If the bit error rate is below the threshold, third data items can be stored as independent second codewords of the same length as the first codewords in the memory cells of the wordline.

Selective and dynamic deployment of error correction code techniques in integrated circuit memory devices

A processing device in a memory sub-system monitors a temperature associated with a block of a memory device, the block comprising a plurality of wordlines. The processing device further determines a first amount of time between when memory cells associated with a first wordline of the plurality of wordlines of the block were written and when memory cells associated with a last wordline of the plurality of wordlines of the block were written. That first amount of time is normalized according to the temperature associated with the block. The processing device further determines, based at last in part on the first amount of time and on an associated scaling factor, an estimate of when the block will reach a uniform charge loss state.

Temperature-compensated time estimate for a block to reach a uniform charge loss state

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Carlsbad, CA, United States of America

Sivagnanam Parthasarathy