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For the Inventor, By the Inventor

Boise, ID, United States of America

Richard H Lane

This inventor holds 88 USPTO granted patents and 1 published patent application and 2 EPO patents, primarily in Semiconductor Processing (CPC class H01L2-18242). Top assignees: Micron Technology Incorporated, Micron Communications, Inc., Round Rock Research, LLC. Active years: 1998-2015.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Richard H Lane. Retrieved from https://idiyas.com/inventor/richard-h-lane

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 88 

% Patents Active = 75.0

 

Average Co-Inventor Count = 2.1

ph-index = 14

Forward Citations = 613(Granted Patents)

Forward Citations (Not Self Cited) = 569(Dec 10, 2025)


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Company Filing History:

goldMedal86 out of 39,222 
 
Micron Technology Incorporated
 patents
silverMedal1 out of 103 
 
Micron Communications, Inc.
 patents
bronzeMedal1 out of 428 
 
Round Rock Research, LLC
 patents

Years Active: 1998-2015

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Areas of Expertise:
Semiconductor Structures
Trench Formation
Electrical Isolation
Integrated Circuits
Electropolishing
Capacitor Constructions
Transistor Gates
Ion Implanting
Noble Metals
Field Emission Device
High-Pressure Anneal
Metal Silicide
88 patents (USPTO):Explore Patents
1. 8987834 - Methods of providing electrical isolation and semiconductor structures including same (2015-03-24),
2. 8685859 - Self-aligned semiconductor trench structures (2014-04-01),
3. 8552526 - Self-aligned semiconductor trench structures (2013-10-08),
4. 8343875 - Methods of forming an integrated circuit with self-aligned trench formation (2013-01-01),
5. 8148775 - Methods of providing electrical isolation and semiconductor structures including same (2012-04-03),
6. 8101497 - Self-aligned trench formation (2012-01-24),
7. 7943477 - Method of patterning noble metals for semiconductor devices by electropolishing (2011-05-17),
8. 7935602 - Semiconductor processing methods (2011-05-03),
9. 7629630 - Electropolished patterned metal layer for semiconductor devices (2009-12-08),
10. 7601598 - Reverse metal process for creating a metal silicide transistor gate structure (2009-10-13),
11. 7501672 - Method and structure for a self-aligned silicided word line and polysilicon plug during the formation of a semiconductor device (2009-03-10),
12. 7473644 - Method for forming controlled geometry hardmasks including subresolution elements (2009-01-06),
13. 7375014 - Methods of electrochemically treating semiconductor substrates (2008-05-20),
14. 7348234 - Methods of forming capacitor constructions (2008-03-25),
15. 7344977 - Method of electroplating a substance over a semiconductor substrate (2008-03-18),

Title: Innovations by Richard H. Lane in Semiconductor Technologies

Introduction

Richard H. Lane is a prominent inventor based in Boise, ID, known for his significant contributions to semiconductor technologies. With an impressive portfolio of 88 patents, Lane has pushed the boundaries of innovation in the semiconductor industry, particularly in methods of electrical isolation and the development of advanced semiconductor structures.

Latest Patents

Two of Richard H. Lane's latest patents demonstrate his expertise in semiconductor technologies. The first patent, titled "Methods of providing electrical isolation and semiconductor structures including same," focuses on techniques for isolating gates within a semiconductor structure. This innovation utilizes spacer material in combination with fins to enhance device performance. Moreover, it capitalizes on the etch characteristics of various materials during fabrication to increase an effective gate length and a field gate oxide, ultimately leading to improved semiconductor structures.

The second patent, "Self-aligned semiconductor trench structures," outlines methods for forming self-aligned trenches that aid in device integration. In this invention, a first set of trenches is utilized to align a second set, allowing for a pitch doubling technique. This method offers advancements in device fabrication, particularly through the employment of a very thin chemical mechanical polishing (CMP) stop layer, which leads to improved planarity at the device surface.

Career Highlights

Throughout his career, Richard H. Lane has been associated with several notable companies, including Micron Technology Incorporated and Micron Communications, Inc. His work in these organizations has greatly contributed to the advancement of semiconductor technologies, solidifying his reputation as a leading inventor in the field.

Collaborations

Richard has collaborated with esteemed professionals in the industry, including John K. Zahurak and Charles H. Dennison. These collaborations have fostered a rich environment of innovation and have led to the successful development of groundbreaking semiconductor technologies.

Conclusion

Richard H. Lane's extensive patent portfolio and innovative spirit mark him as a significant figure in the semiconductor industry. His recent patents continue to pave the way for advancements in electrical isolation and trench structures, making a lasting impact on the future of semiconductor technologies.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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