logo

For the Inventor, By the Inventor

Mount Kisco, NY, United States of America

Pranita Kerber

This inventor holds 94 USPTO granted patents and 7 published patent applications, primarily in Semiconductor Devices (CPC class H01L29-66545). Top assignees: International Business Machines Corporation, Globalfoundries Inc., Globalfoundries U.S. 2 LLC. Active years: 2013-2021.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Pranita Kerber. Retrieved from https://idiyas.com/inventor/pranita-kerber

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 94 

% Patents Active = 50.0

Average Co-Inventor Count = 4.0

ph-index = 7

Forward Citations = 551(Granted Patents)

Forward Citations (Not Self Cited) = 524(Dec 10, 2025)


Inventors with similar research interests:

🔬 See more inventors

Location History:

  • Albany, NY (US) (2013)
  • Yorktown Heights, NY (US) (2014)
  • Singerlands, NY (US) (2015)
  • Slingerlands, NY (US) (2014 - 2017)
  • Armonk, NY (US) (2017)
  • Mount Kisco, NY (US) (2013 - 2021)

Company Filing History:

goldMedal76 out of 166,409 
 
International Business Machines Corporation
 patents
silverMedal17 out of 5,671 
 
Globalfoundries Inc.
 patents
bronzeMedal1 out of 59 
 
Globalfoundries U.S. 2 LLC
 patents
4. 1 out of 7,657 
 
Renesas Electronics Corporation
 patents
where one patent can have more than one assignee

Years Active: 2013-2021

Loading Chart...
Areas of Expertise:
FinFET Technology
High-K Dielectrics
III-V Transistors
Gate Dielectric
Silicon Germanium
Short-Channel MOSFET
Buried Channel Region
Epitaxy
Tensile Strain
Reduced Leakage
Transistor Structure
Integrated Circuits
94 patents (USPTO):Explore Patents
1. 10957780 - Non-uniform gate dielectric for U-shape MOSFET (2021-03-23),
2. 10937871 - III-V transistor device with self-aligned doped bottom barrier (2021-03-02),
3. 10680085 - Transistor structure with varied gate cross-sectional area (2020-06-09),
4. 10643907 - Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step (2020-05-05),
5. 10374042 - Semiconductor device including epitaxially formed buried channel region (2019-08-06),
6. 10262999 - High-k gate dielectric and metal gate conductor stack for fin-type field effect transistors formed on type III-V semiconductor material and silicon germanium semiconductor material (2019-04-16),
7. 10256319 - Non-uniform gate dielectric for U-shape MOSFET (2019-04-09),
8. 10217745 - High-K gate dielectric and metal gate conductor stack for fin-type field effect transistors formed on type III-V semiconductor material and silicon germanium semiconductor material (2019-02-26),
9. 10204837 - Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step (2019-02-12),
10. 10192888 - Metallized junction FinFET structures (2019-01-29),
11. 10176990 - SiGe FinFET with improved junction doping control (2019-01-08),
12. 10002871 - High-K gate dielectric and metal gate conductor stack for fin-type field effect transistors formed on type III-V semiconductor material and silicon germanium semiconductor material (2018-06-19),
13. 10002798 - Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step (2018-06-19),
14. 9972711 - Reduced resistance short-channel InGaAs planar MOSFET (2018-05-15),
15. 9966457 - Transistor structure with varied gate cross-sectional area (2018-05-08),

Title: The Innovative Journey of Pranita Kerber

Introduction

Pranita Kerber, based in Mount Kisco, NY, is a celebrated inventor with an impressive portfolio of 94 patents. Known for her groundbreaking advancements in semiconductor technology, Kerber has made significant contributions that have the potential to reshape the future of electronics.

Latest Patents

Among her recent innovations are two notable patents. The first is a "Non-uniform gate dielectric for U-shape MOSFET," which presents a U-shaped gate dielectric structure designed to minimize capacitance through a unique configuration of horizontal and vertical dielectric portions. The second patent, titled "III-V transistor device with self-aligned doped bottom barrier," details a sophisticated semiconductor device that incorporates a doped III-V semiconductor material barrier.

Career Highlights

Pranita Kerber has built her career at prestigious organizations such as International Business Machines Corporation (IBM) and Globalfoundries Inc. Her work within these companies has solidified her reputation as a pioneer in the field of semiconductor development, leading to numerous innovations that enhance the performance and efficiency of electronic devices.

Collaborations

Throughout her career, Kerber has collaborated with several esteemed professionals, including Alexander Reznicek and Ali Khakifirooz. These collaborations have not only enriched her work but also fostered an environment of innovation and creativity, leading to the development of cutting-edge technologies.

Conclusion

Pranita Kerber's contributions to the field of semiconductor technology through her patents reflect her commitment to innovation. Her work continues to inspire the next generation of inventors and engineers, ensuring her legacy in the world of technology will endure.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…