The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 08, 2018

Filed:

Mar. 18, 2016
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Dominic J. Schepis, Wappingers Falls, NY (US);

Alexander Reznicek, Troy, NY (US);

Pranita Kerber, Mount Kisco, NY (US);

Qiqing C. Ouyang, Yorktown Heights, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 21/321 (2006.01); H01L 21/306 (2006.01); H01L 21/324 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66818 (2013.01); H01L 21/30604 (2013.01); H01L 21/321 (2013.01); H01L 21/324 (2013.01); H01L 21/76897 (2013.01); H01L 29/42356 (2013.01); H01L 29/66545 (2013.01); H01L 29/785 (2013.01);
Abstract

Aspects of the present disclosure include finFET structures with varied cross-sectional areas and methods of forming the same. Methods according to the present disclosure can include, e.g., forming a structure including: a semiconductor fin positioned on a substrate, wherein the semiconductor fin includes: a gate area, and a terminal area laterally distal to the gate area, a sacrificial gate positioned on the gate area of the semiconductor fin, and an insulator positioned on the terminal area of the semiconductor fin; removing the sacrificial gate to expose the gate area of the semiconductor fin; increasing or reducing a cross-sectional area of the gate area of the semiconductor fin; and forming a transistor gate on the gate area of the semiconductor fin.


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