International Business Machines Corporation

Globalfoundries Inc.

Renesas Electronics Corporation

Globalfoundries U.S. 2 LLC

Pranita Kerber

Alexander Reznicek

Ali Khakifirooz

Kangguo Cheng

Qiqing Christine Ouyang

Bruce Bennett Doris

Effendi Leobandung

Dominic Joseph Schepis

Cheng-Wei Cheng

Takashi Ando

Yanning Sun

Vijay Narayanan

Amlan Majumdar

Martin Michael Frank

Veeraraghavan S Basker

Ghavam G Shahidi

Keith E Fogel

Jie Deng

Chun-chen Yeh

Shom Ponoth

Christian Lavoie

Joshua M Rubin

Balasubramanian S Haran

Young-Hee Kim

Pouya Hashemi

Tenko Yamashita

Junli Wang

Rajiv V Joshi

Tak H Ning

Balasubramanian Pranatharthiharan

Terence B Hook

Arvind Kumar

Subramanian Srikanteswara Iyer

Renee Tong Mo

Viorel C Ontalus

Philip Joseph Oldiges

Raghavasimhan Sreenivasan

Rouwaida N Kanj

Donald Rene Wall

Zhengmao Zhu

Carl John Radens

Stephen W Bedell

Steven J Holmes

Jeffrey W Sleight

Shogo Mochizuki

Judson Robert Holt

Chung-Hsun Lin

Jin Cai

Douglas C La Tulipe, Jr

Gen Tsutsui

Stefan Schmitz

Lisa F Edge

Christine Qiqing Ouyang

Sudesh Saroop

Qiping C Ouyang

Tanko Yamashita

A U-shaped gate dielectric structure is provided that has a horizontal gate dielectric portion having a vertical thickness, and a vertical gate dielectric wall portion extending upwards from the horizontal gate dielectric portion. The vertical gate dielectric wall portion has a lateral thickness that is greater than the vertical thickness of the horizontal gate dielectric portion. The U-shaped gate dielectric structure houses a gate conductor portion. Collectively, the U-shaped gate dielectric structure and the gate conductor portion provide a functional gate structure that has reduced capacitance.

Non-uniform gate dielectric for U-shape MOSFET

A semiconductor device comprises a first layer of a substrate arranged on a second layer of the substrate the second layer of the substrate including a doped III-V semiconductor material barrier layer, a gate stack arranged on a channel region of the first layer of a substrate, a spacer arranged adjacent to the gate stack on the first layer of the substrate, an undoped epitaxially grown III-V semiconductor material region arranged on the second layer of the substrate, and an epitaxially grown source/drain region arranged on the undoped epitaxially grown III-V semiconductor material region, and a portion of the first layer of the substrate.

III-V transistor device with self-aligned doped bottom barrier

Aspects of the present disclosure include finFET structures with varied cross-sectional areas and methods of forming the same. Methods according to the present disclosure can include, e.g., forming a structure including: a semiconductor fin positioned on a substrate, wherein the semiconductor fin includes: a gate area, and a terminal area laterally distal to the gate area, a sacrificial gate positioned on the gate area of the semiconductor fin, and an insulator positioned on the terminal area of the semiconductor fin; removing the sacrificial gate to expose the gate area of the semiconductor fin; increasing or reducing a cross-sectional area of the gate area of the semiconductor fin; and forming a transistor gate on the gate area of the semiconductor fin.

Transistor structure with varied gate cross-sectional area

A method of making a semiconductor device includes forming a first silicon germanium layer on a substrate, the first silicon germanium layer forming a portion of a first transistor; forming a second silicon germanium layer on the substrate adjacent to the first silicon germanium layer, the second silicon germanium layer forming a portion of a second transistor and having a germanium content that is different than the first silicon germanium layer and a thickness that is substantially the same; growing by an epitaxial process a compressively strained silicon germanium layer on the first silicon germanium layer, and a tensile strained silicon germanium layer on the second silicon germanium layer; patterning a first fin in the compressively strained silicon germanium layer and the first silicon germanium layer; and patterning a second fin in the tensile strained silicon germanium layer and the second silicon germanium layer.

Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step

A semiconductor device includes at least one semiconductor fin on an upper surface of a substrate. The at least one semiconductor fin includes a channel region interposed between opposing source/drain regions. A gate stack is on the upper surface of the substrate and wraps around sidewalls and an upper surface of only the channel region. The channel region is a dual channel region including a buried channel portion and a surface channel portion that completely surrounds the buried channel.

Semiconductor device including epitaxially formed buried channel region

An electrical device that includes at least one n-type field effect transistor including a channel region in a type III-V semiconductor device, and at least one p-type field effect transistor including a channel region in a germanium containing semiconductor material. Each of the n-type and p-type semiconductor devices may include gate structures composed of material layers including work function adjusting materials selections, such as metal and doped dielectric layers. The field effect transistors may be composed of fin type field effect transistors. The field effect transistors may be formed using gate first processing or gate last processing.

High-k gate dielectric and metal gate conductor stack for fin-type field effect transistors formed on type III-V semiconductor material and silicon germanium semiconductor material

High-K gate dielectric and metal gate conductor stack for fin-type field effect transistors formed on type III-V semiconductor material and silicon germanium semiconductor material

FinFET devices are provided wherein the current path is minimized and mostly limited to spacer regions before the channel carriers reach the metal contacts. The fins in the source/drain regions are metallized to increase the contact area and reduce contact resistance. Selective removal of semiconductor fins in the source/drain regions following source/drain epitaxy facilitates replacement thereof by the metallized fins. A spacer formed subsequent to source/drain epitaxy prevents the etching of extension/channel regions during semiconductor fin removal.

Metallized junction FinFET structures

A semiconductor device and a method for fabricating the device. The method includes: providing a FinFET having a source/drain region, at least one SiGe fin, a silicon substrate, a local oxide layer is formed on the silicon substrate, a gate structure is formed on the at least one SiGe fin and the local oxide layer, the gate structure is encapsulated by a gate hard mask and sidewall spacer layers; recessing the at least one SiGe fin in the source/drain region to the sidewall spacer layers and the silicon substrate layer; recessing the local oxide layer in the source/drain region to the sidewall spacer layer and the silicon substrate; growing a n-doped silicon layer on the silicon substrate; growing a p-doped silicon layer or p-doped SiGe layer on the n-doped silicon layer; and forming a silicide layer on the p-doped silicon layer or p-doped SiGe layer.

SiGe FinFET with improved junction doping control

A metal-oxide-semiconductor field effect transistor (MOSFET) and a method of fabricating a MOSFET are described. The method includes depositing and patterning a dummy gate stack above an active channel layer formed on a base. The method also includes selectively etching the active channel layer leaving a remaining active channel layer, and epitaxially growing silicon doped active channel material adjacent to the remaining active channel layer.

Reduced resistance short-channel InGaAs planar MOSFET

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Mount Kisco, NY, United States of America

Pranita Kerber