The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 08, 2019

Filed:

Aug. 19, 2016
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Pranita Kerber, Mount Kisco, NY (US);

Qiqing C. Ouyang, Yorktown Heights, NY (US);

Alexander Reznicek, Troy, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 21/306 (2006.01); H01L 29/78 (2006.01); H01L 29/165 (2006.01); H01L 21/285 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/161 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02694 (2013.01); H01L 21/0245 (2013.01); H01L 21/02532 (2013.01); H01L 21/02579 (2013.01); H01L 21/28518 (2013.01); H01L 21/306 (2013.01); H01L 29/0638 (2013.01); H01L 29/0653 (2013.01); H01L 29/0847 (2013.01); H01L 29/1054 (2013.01); H01L 29/161 (2013.01); H01L 29/165 (2013.01); H01L 29/66636 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7848 (2013.01); H01L 29/7851 (2013.01);
Abstract

A semiconductor device and a method for fabricating the device. The method includes: providing a FinFET having a source/drain region, at least one SiGe fin, a silicon substrate, a local oxide layer is formed on the silicon substrate, a gate structure is formed on the at least one SiGe fin and the local oxide layer, the gate structure is encapsulated by a gate hard mask and sidewall spacer layers; recessing the at least one SiGe fin in the source/drain region to the sidewall spacer layers and the silicon substrate layer; recessing the local oxide layer in the source/drain region to the sidewall spacer layer and the silicon substrate; growing a n-doped silicon layer on the silicon substrate; growing a p-doped silicon layer or p-doped SiGe layer on the n-doped silicon layer; and forming a silicide layer on the p-doped silicon layer or p-doped SiGe layer.


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