Paul A Ingersoll

This inventor holds 16 USPTO granted patents. Top assignees: Freescale Semiconductor,inc., Motorola Corporation. Active years: 2002-2013.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Paul A Ingersoll. Retrieved from https://idiyas.com/inventor/paul-a-ingersoll

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 16

% Patents Active = 56.3

Average Co-Inventor Count = 2.9

ph-index = 7

Forward Citations = 325(Granted Patents)

Company Filing History:

13 out of 5,491

Freescale Semiconductor,inc.

Years Active: 2002-2013

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16 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 8435898 - First inter-layer dielectric stack for non-volatile memory (2013-05-07),

2. 7642594 - Electronic device including gate lines, bit lines, or a combination thereof (2010-01-05),

3. 7619270 - Electronic device including discontinuous storage elements (2009-11-17),

4. 7592224 - Method of fabricating a storage device including decontinuous storage elements within and between trenches (2009-09-22),

5. 7491600 - Nanocrystal bitcell process integration for high density application (2009-02-17),

6. 7432547 - Non-volatile memory device with improved data retention and method therefor (2008-10-07),

7. 7259999 - Non-volatile memory cell array for improved data retention and method of operating thereof (2007-08-21),

8. 7211487 - Process for forming an electronic device including discontinuous storage elements (2007-05-01),

9. 7208390 - Semiconductor device structure and method for forming (2007-04-24),

10. 6991984 - Method for forming a memory structure using a modified surface topography and structure thereof (2006-01-31),

11. 6898129 - Erase of a memory having a non-conductive storage medium (2005-05-24),

12. 6887758 - Non-volatile memory device and method for forming (2005-05-03),

13. 6770929 - Method for uniform polish in microelectronic device (2004-08-03),

14. 6713812 - Non-volatile memory device having an anti-punch through (APT) region (2004-03-30),

15. 6518146 - Semiconductor device structure and method for forming (2003-02-11),

Title: Paul A. Ingersoll: Innovator in Non-Volatile Memory Technology

Introduction

Paul A. Ingersoll is a prominent inventor based in Austin, TX, known for his significant contributions to the field of non-volatile memory technology. With a total of 16 patents to his name, Ingersoll has made a lasting impact on the electronics industry through his innovative designs and methods.

Latest Patents

Among his latest patents is a groundbreaking method for forming a first inter-layer dielectric (ILD0) stack that includes a protective gettering layer with a substantially uniform thickness. This invention involves the deposition of a gap fill dielectric layer of SATEOS over an etch stop layer of PEN ESL, followed by the sequential deposition of a gettering layer of BPTEOS and a capping dielectric layer. Additionally, he has developed an electronic device that incorporates memory cells connected to gate lines and bit lines, allowing for efficient orientation and connection of memory cells.

Career Highlights

Ingersoll has had a distinguished career, working with leading companies such as Freescale Semiconductor, Inc. and Motorola Corporation. His work has been instrumental in advancing memory technology, making him a respected figure in the industry.

Collaborations

Throughout his career, Ingersoll has collaborated with notable colleagues, including Gowrishankar L. Chindalore and Craig T. Swift. These partnerships have contributed to the development of innovative solutions in the field of electronics.

Conclusion

Paul A. Ingersoll's contributions to non-volatile memory technology and his extensive patent portfolio highlight his role as a key innovator in the electronics industry. His work continues to influence advancements in memory technology and electronic devices.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]