Freescale Semiconductor,inc.

Motorola Corporation

Paul A Ingersoll

Gowrishankar L Chindalore

Craig T Swift

Rana P Singh

Alexander Hoefler

Frank Kelsey Baker, Jr

Erwin J Prinz

Criag T Swift

Ramachandran Muralidhar

Olubunmi O Adetutu

Ronald J Syzdek

Peter J Kuhn

Christopher B Hundley

A method and apparatus are described for forming a first inter-layer dielectric (ILD0) stack having a protective gettering layer () with a substantially uniform thickness. After forming device components () on a substrate (), a gap fill dielectric layer of SATEOS () is deposited over an etch stop layer of PEN ESL () and then planarized before sequentially depositing a gettering layer of BPTEOS () and capping dielectric layer () on the planarized gap fill dielectric layer (). Once the ILD0 stack is formed, one or more contact openings () are etched through the ILD0 stack, thereby exposing the etch stop layer () over the intended contact regions.

First inter-layer dielectric stack for non-volatile memory

An electronic device can include memory cells that are connected to gate lines, bit lines, or a combination thereof. In one embodiment, at least two sets of memory cells can be oriented substantially along a first direction, (e.g., rows or columns). A first gate line may be electrically connected to fewer rows or columns of memory cells as compared to a second gate line. For example, the first gate line may only be electrically connected to the first set of memory cells, and the second gate line may be electrically connected to the second and third sets of memory cells. In another embodiment, a first bit line may be electrically connected to fewer rows or columns of memory cells as compared to a second bit line. In still another embodiment, another set of memory cells may be oriented substantially along another direction that is substantially perpendicular to the first direction.

Electronic device including gate lines, bit lines, or a combination thereof

An electronic device can include discontinuous storage elements that lie within a trench. The electronic device can include a substrate including a trench that includes a wall and a bottom and extends from a primary surface of the substrate. The electronic device can also include discontinuous storage elements, wherein a portion of the discontinuous storage elements lies at least within the trench. The electronic device can further include a first gate electrode, wherein at least a part of the portion of the discontinuous storage elements lies between the first gate electrode and the wall of the trench. The electronic device can still further include a second gate electrode overlying the first gate electrode and the primary surface of the substrate.

Electronic device including discontinuous storage elements

A semiconductor storage cell includes a first source/drain region underlying a first trench defined in a semiconductor layer. A second source/drain region underlies a second trench in the semiconductor layer. A first select gate in the first trench and a second select gate in the second trench are lined by a select gate dielectric. A charge storage stack overlies the select gates and a control gate overlies the stack. The DSEs may comprise discreet accumulations of polysilicon. An upper surface of the first and second select gates is lower than an upper surface of the first and second trenches. The control gate may be a continuous control gate traversing and running perpendicular to the select gates. The cell may include contacts to the semiconductor layer. The control gate may include a first control gate overlying the first select gate and a second control gate overlying the second select gate.

Method of fabricating a storage device including decontinuous storage elements within and between trenches

A method for making a multibit non-volatile memory cell structure is provided herein. In accordance with the method, a semiconductor substrate () is provided, and first and second sets of memory stacks (, and) are formed on the substrate, each memory stack including a control gate () and a layer of memory material (). A source/drain region () is then formed between the first and second sets of memory stacks, and a silicide layer () is formed over the source/drain region.

Nanocrystal bitcell process integration for high density application

A semiconductor device () comprises an underlying insulating layer (), an overlying insulating layer () and a charge storage layer () between the insulating layers (). The charge storage layer () and the overlying insulating layer () form an interface, where at least a majority of charge in the charge storage layer () is stored. This can be accomplished by forming a charge storage layer () with different materials such as silicon and silicon germanium layers or n-type and p-type material layers, in one embodiment. In another embodiment, the charge storage layer () comprises a dopant that is graded. By storing at least a majority of the charge at the interface between the charge storage layer () and the overlying insulating layer (), the leakage of charge through the underlying insulating layer is decreased allowing for a thinner underlying insulating layer () to be used.

Non-volatile memory device with improved data retention and method therefor

A method is provided which includes erasing a first plurality of non-volatile memory bit cells in a memory block comprising a third plurality of memory bit cells during an erase procedure, such that upon completion of the erase procedure, the first plurality of non-volatile memory bit cells are at an erased state. The method also includes programming a second plurality of non-volatile memory bit cells in the memory block during the erase procedure, such that the second plurality of non-volatile memory bit cells is a subset of the third plurality of non-volatile memory bit cells and upon completion of the erase procedure, the second plurality of non-volatile memory bit cells are at a programmed state.

Non-volatile memory cell array for improved data retention and method of operating thereof

A process for forming an electronic device can include forming a first trench within a substrate, wherein the trench includes a wall and a bottom and extends from a primary surface of the substrate. The process can also include forming discontinuous storage elements and forming a first gate electrode within the trench such that, a first discontinuous storage element of the discontinuous storage elements lies between the first gate electrode and the wall of the trench. The process can further include removing the discontinuous storage elements that overlie the primary surface of the substrate. The process can still further include forming a second gate electrode that overlies the first gate electrode and the primary surface of the substrate.

Process for forming an electronic device including discontinuous storage elements

A semiconductor device structure has trenches of two widths or more. The smallest widths are to maximize density. The greater widths may be required because of more demanding isolation, for example, in the case of non-volatile memories. These more demanding, wider isolation trenches are lined with a high quality grown oxide as part of the process for achieving the desired result of high quality isolation. For the case of the narrowest trenches, the additional liner causes the aspect ratio, the ratio of the depth of the trench to the width of the trench, to increase. Subsequent deposition of insulating material to fill the trenches with the highest aspect ratios can result in voids that can ultimately result in degraded yields. These voids are avoided by etching at least a portion of the liners of those trenches with the highest aspect ratios to reduce the aspect ratio to acceptable levels.

Semiconductor device structure and method for forming

To increase the gate coupling ratio of a semiconductor device, discrete elements, such as nanocrystals, are deposited over a floating gate. In one embodiment, the discrete elementsare pre-formed in a vapor phase and are attached to the semiconductor deviceby electrostatic force. In one embodiment, the discrete elementsare pre-formed in a different chamber than that where they are attached. In another embodiment, the same chamber is used for the entire deposition process. An optional, interfacial layermay be formed between the floating gateand the discrete elements

Method for forming a memory structure using a modified surface topography and structure thereof

A non volatile memory includes a plurality of transistors having a non conductive storage medium. The transistors are erased by injecting holes into the storage medium from both the source edge region and drain edge region of the transistor. In one example, the storage medium is made from silicon nitride isolated from the underlying substrate and overlying gate by silicon dioxide. The injection of holes in the storage medium generates two hole distributions having overlapping portions. The combined distribution of the overlapping portions is above at least a level of the highest concentration of program charge in the overlap region of the storage medium. In one example, the transistors are programmed by hot carrier injection. In some examples, the sources of groups of transistors of the memory are decoded.

Erase of a memory having a non-conductive storage medium

A semiconductor device () has a highly doped layer () having a first conductivity type uniformly implanted into the semiconductor substrate (). An oxide-nitride-oxide structure () is formed over the semiconductor substrate (). A halo region () having the first conductivity type is implanted at an angle in only a drain side of the oxide-nitride-oxide structure and extends under the oxide-nitride-oxide structure a predetermined distance from an edge of the oxide-nitride-oxide structure. A source () and drain () having a second conductivity type are implanted into the substrate (). The resulting non-volatile memory cell provides a low natural threshold voltage to minimize threshold voltage drift during a read cycle. In addition, the use of the halo region () on the drain side allows a higher programming speed, and the highly doped layer () allows the use of a short channel device.

Non-volatile memory device and method for forming

A method for achieving a uniform planar surface by a chemical mechanical polish includes surrounding an active area or array to be polished with a border of the active material such that the border is wider than a single active area within the array and is preferably spaced from the outermost active area by the same distance as the distance between active areas within the array.

Method for uniform polish in microelectronic device

A memory device ( ) that uses a non-volatile storage element ( ), such as nitride, has reduced read disturb, which is the problem of tending to increase the threshold voltage of a memory device ( ) during a read. To reduce this effect, the memory device ( ) uses a counterdoped channel ( ) to lower the natural threshold voltage of the device ( ). This counterdoping can even be of sufficient dosage to reverse the conductivity type of the channel ( ) and causing a negative natural threshold voltage. This allows for a lower gate voltage during read to reduce the adverse effect of performing a read. An anti-punch through (ATP) region ( ) below the channel ( ) allows for the lightly doped or reversed conductivity type channel ( ) to avoid short channel leakage. A halo implant ( ) on the drain side ( ) assists in hot carrier injection (HCI) so that the HCI is effective even though the channel ( ) is lightly doped or of reversed conductivity type.

Non-volatile memory device having an anti-punch through (APT) region

A semiconductor device has both a logic section and a non-volatile memory (NVM) section. Transistors in both sections are separated by trench isolation. The logic isolation has narrower trenches than NVM trenches and both types of trenches have corners at the tops thereof. The trenches are lined by growing an oxide that is necessarily to take care of the plasma damage of the substrate, which is preferably silicon, that occurs during the formation of the trenches. These oxide liners are grown to a greater thickness in the NVM trenches than in the logic trenches to obtain a greater degree of corner rounding in the NVM trenches. This growth differential is achieved by selectively implanting the NVM trenches with a species that speeds oxide growth or selectively implanting the logic trenches with a species that retards oxide growth. As a further alternative, the NVM trenches can be implanted with a growth enhancing species and the logic trenches with a retarding species.

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Austin, TX, United States of America

Paul A Ingersoll