The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 07, 2008
Filed:
Feb. 13, 2004
Gowrishankar L. Chindalore, Austin, TX (US);
Frank K. Baker, Jr., Austin, TX (US);
Paul A. Ingersoll, Austin, TX (US);
Alexander B. Hoefler, Austin, TX (US);
Gowrishankar L. Chindalore, Austin, TX (US);
Frank K. Baker, Jr., Austin, TX (US);
Paul A. Ingersoll, Austin, TX (US);
Alexander B. Hoefler, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A semiconductor device () comprises an underlying insulating layer (), an overlying insulating layer () and a charge storage layer () between the insulating layers (). The charge storage layer () and the overlying insulating layer () form an interface, where at least a majority of charge in the charge storage layer () is stored. This can be accomplished by forming a charge storage layer () with different materials such as silicon and silicon germanium layers or n-type and p-type material layers, in one embodiment. In another embodiment, the charge storage layer () comprises a dopant that is graded. By storing at least a majority of the charge at the interface between the charge storage layer () and the overlying insulating layer (), the leakage of charge through the underlying insulating layer is decreased allowing for a thinner underlying insulating layer () to be used.