The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2006

Filed:

Jan. 27, 2004
Applicants:

Paul A. Ingersoll, Austin, TX (US);

Gowrishankar L. Chindalore, Austin, TX (US);

Ramachandran Muralidhar, Austin, TX (US);

Inventors:

Paul A. Ingersoll, Austin, TX (US);

Gowrishankar L. Chindalore, Austin, TX (US);

Ramachandran Muralidhar, Austin, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

To increase the gate coupling ratio of a semiconductor device, discrete elements, such as nanocrystals, are deposited over a floating gate. In one embodiment, the discrete elementsare pre-formed in a vapor phase and are attached to the semiconductor deviceby electrostatic force. In one embodiment, the discrete elementsare pre-formed in a different chamber than that where they are attached. In another embodiment, the same chamber is used for the entire deposition process. An optional, interfacial layermay be formed between the floating gateand the discrete elements


Find Patent Forward Citations

Ingersoll, Paul. (2006). Method for forming a memory structure using a modified surface topography and structure thereof (U.S. Patent No. 6991984). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6991984

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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