The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 21, 2007

Filed:

Oct. 26, 2005
Applicants:

Ronald J. Syzdek, Austin, TX (US);

Gowrishankar L. Chindalore, Austin, TX (US);

Paul A. Ingersoll, Austin, TX (US);

Peter J. Kuhn, Austin, TX (US);

Inventors:

Ronald J. Syzdek, Austin, TX (US);

Gowrishankar L. Chindalore, Austin, TX (US);

Paul A. Ingersoll, Austin, TX (US);

Peter J. Kuhn, Austin, TX (US);

Assignee:

Freescale Semiconductor, Inc, Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method is provided which includes erasing a first plurality of non-volatile memory bit cells in a memory block comprising a third plurality of memory bit cells during an erase procedure, such that upon completion of the erase procedure, the first plurality of non-volatile memory bit cells are at an erased state. The method also includes programming a second plurality of non-volatile memory bit cells in the memory block during the erase procedure, such that the second plurality of non-volatile memory bit cells is a subset of the third plurality of non-volatile memory bit cells and upon completion of the erase procedure, the second plurality of non-volatile memory bit cells are at a programmed state.


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