Method of fabricating a storage device including decontinuous storage elements within and between trenches

Abstract

A semiconductor storage cell includes a first source/drain region underlying a first trench defined in a semiconductor layer. A second source/drain region underlies a second trench in the semiconductor layer. A first select gate in the first trench and a second select gate in the second trench are lined by a select gate dielectric. A charge storage stack overlies the select gates and a control gate overlies the stack. The DSEs may comprise discreet accumulations of polysilicon. An upper surface of the first and second select gates is lower than an upper surface of the first and second trenches. The control gate may be a continuous control gate traversing and running perpendicular to the select gates. The cell may include contacts to the semiconductor layer. The control gate may include a first control gate overlying the first select gate and a second control gate overlying the second select gate.