The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 03, 2005
Filed:
Oct. 09, 2002
Gowrishankar L. Chindalore, Austin, TX (US);
Paul A. Ingersoll, Austin, TX (US);
Craig T. Swift, Austin, TX (US);
Alexander B. Hoefler, Austin, TX (US);
Gowrishankar L. Chindalore, Austin, TX (US);
Paul A. Ingersoll, Austin, TX (US);
Craig T. Swift, Austin, TX (US);
Alexander B. Hoefler, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A semiconductor device () has a highly doped layer () having a first conductivity type uniformly implanted into the semiconductor substrate (). An oxide-nitride-oxide structure () is formed over the semiconductor substrate (). A halo region () having the first conductivity type is implanted at an angle in only a drain side of the oxide-nitride-oxide structure and extends under the oxide-nitride-oxide structure a predetermined distance from an edge of the oxide-nitride-oxide structure. A source () and drain () having a second conductivity type are implanted into the substrate (). The resulting non-volatile memory cell provides a low natural threshold voltage to minimize threshold voltage drift during a read cycle. In addition, the use of the halo region () on the drain side allows a higher programming speed, and the highly doped layer () allows the use of a short channel device.