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For the Inventor, By the Inventor

Hsinchu, Taiwan

Meng-Liang Lin

This inventor holds 50 USPTO granted patents and 51 published patent applications, primarily in Semiconductor Packaging. Top assignees: Taiwan Semiconductor Manufacturing Comp. Ltd., Taiwan Semiconductor Manufacturing Co., Ltd.. Active years: 2016-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Meng-Liang Lin. Retrieved from https://idiyas.com/inventor/meng-liang-lin

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 50 

% Patents Active = 88.0

Average Co-Inventor Count = 4.6

ph-index = 6

Forward Citations = 73(Granted Patents)


Company Filing History:

goldMedal48 out of 42,810 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents
silverMedal2 out of 465 
 
Taiwan Semiconductor Manufacturing Co., Ltd.
 patents

Years Active: 2016-2026

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Areas of Expertise:
Semiconductor Packaging
Fan-Out Structure
Integrated Passive Devices
Routing Density
Chip Package
Interposer Structure
Cavity Substrate
Stress Control Layer
RF Isolation
Dual-Sided Routing
Conductive Via
Redistribution Structure
50 patents (USPTO):Explore Patents
1. 12745645 - Integrated circuit packages and methods of forming the same (2026-09-22),
2. 12707947 - Structures for reducing gap fill defects in a vertically stacked semiconductor device and methods for forming the same (2026-08-11),
3. 12702078 - Redistribution structure with copper bumps on planar metal interconnects and methods of forming the same (2026-08-04),
4. 12702060 - Package and method for forming the same (2026-08-04),
5. 12642097 - Semiconductor package having conductive layer covering back surfaces of dies and manufacturing method of semiconductor package (2026-05-26),
6. 12635509 - Package structure (2026-05-19),
7. 12622314 - Dam structure for integrated passive device integration and methods of forming the same (2026-05-05),
8. 12604765 - Integrated passive device dies and methods of forming and placement of the same (2026-04-14),
9. 12564076 - Chip package with fan-out feature and method for forming the same (2026-02-24),
10. 12538819 - Inductor RF isolation structure in an interposer and methods of forming the same (2026-01-27),
11. 12532771 - Package structure with fan-out feature (2026-01-20),
12. 12512382 - Semiconductor device including stress control layer and methods of forming the same (2025-12-30),
13. 12489029 - Redistribution structure with warpage tuning layer (2025-12-02),
14. 12444663 - Semiconductor package including a semiconductor die disposed in a cavity and method for manufacturing thereof (2025-10-14),
15. 12368109 - Interposer structure for semiconductor package including peripheral metal pad around alignment mark and methods of fabricating same (2025-07-22),

Title: The Innovative Journey of Inventor Meng-Liang Lin

Introduction: Meng-Liang Lin, a talented inventor hailing from Hsinchu, Taiwan, has made significant contributions to the field of technology with his groundbreaking innovations.

Latest Patents: Lin's latest patents showcase his prowess in developing cutting-edge solutions for various industries, including electronics, telecommunications, and renewable energy.

Career Highlights: Throughout his illustrious career, Meng-Liang Lin has been recognized for his exceptional problem-solving skills and creativity, leading to the successful development of numerous patented inventions that have revolutionized the way we live and work.

Collaborations: Lin has collaborated with top research institutions, universities, and leading companies to further enhance his inventions and bring them to the market, solidifying his reputation as a visionary inventor.

Conclusion: Meng-Liang Lin's passion for innovation and his relentless pursuit of excellence have established him as a prominent figure in the world of inventions, inspiring future generations to push the boundaries of what is possible.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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