The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2026

Filed:

Jan. 09, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Hsien-Wei Chen, Hsinchu, TW;

Chieh-Lung Lai, Taichung City, TW;

Meng-Liang Lin, Hsinchu, TW;

Chun-Yueh Yang, Taipei City, TW;

Shin-Puu Jeng, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/66 (2006.01); H10B 80/00 (2023.01); H10W 42/20 (2026.01); H10W 44/20 (2026.01); H10W 70/05 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 90/00 (2026.01); H10W 70/655 (2026.01); H10W 72/00 (2026.01); H10W 74/15 (2026.01);
U.S. Cl.
CPC ...
H10W 44/20 (2026.01); H10B 80/00 (2023.02); H10W 42/20 (2026.01); H10W 70/05 (2026.01); H10W 70/093 (2026.01); H10W 70/095 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 90/401 (2026.01); H10W 90/701 (2026.01); H10W 44/209 (2026.01); H10W 44/241 (2026.01); H10W 70/655 (2026.01); H10W 72/0198 (2026.01); H10W 74/15 (2026.01); H10W 90/724 (2026.01); H10W 90/734 (2026.01);
Abstract

An integrated circuit package includes an interposer, the interposer including: a first redistribution layer, a second redistribution layer over the first redistribution layer in a central region of the interposer, a dielectric layer over the first redistribution layer in a periphery of the interposer, the dielectric layer surrounding the second redistribution layer in a top-down view, a third redistribution layer over the second redistribution layer and the dielectric layer, and a first direct via extending through the dielectric layer. A conductive feature of the third redistribution layer is coupled to a conductive feature of the first redistribution layer through the first direct via.


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